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IS62WV5128DALL の電気的特性と機能

IS62WV5128DALLのメーカーはISSIです、この部品の機能は「ULTRA LOW POWER CMOS STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS62WV5128DALL
部品説明 ULTRA LOW POWER CMOS STATIC RAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS62WV5128DALL Datasheet, IS62WV5128DALL PDF,ピン配置, 機能
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
512K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM F EB R U ARY 2012
FEATURES
• High-speed access time: 35, 45, 55 ns
• CMOS low power operation
36 mW (typical) operating
9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
1.65V – 2.2V Vdd (IS62WV5128DALL)
2.3V – 3.6V Vdd (IS62WV5128DBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and Automotive temperature support
• Lead-free available
DESCRIPTION
The ISSI IS62WV5128DALL / IS62WV5128DBLL are
high-speed, 4M bit static RAMs organized as 512K words
by 8 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV5128DALL and IS62WV5128DBLL are
packaged in the JEDEC standard 32-pin TSOP (TYPE
I), 32-pin sTSOP (TYPE I), 32-pin TSOP (Type II), 32-pin
SOP and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
VDD
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
512K x 8
MEMORY ARRAY
COLUMN I/O
CS1
OE
WE
CONTROL
CIRCUIT
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  A
02/09/2012
1

1 Page





IS62WV5128DALL pdf, ピン配列
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
PIN DESCRIPTIONS
A0-A18 Address Inputs
CS1 Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Vdd Power
GND Ground
PIN CONFIGURATION
32-pin TSOP (TYPE I), (Package Code T)
32-pin sTSOP (TYPE I) (Package Code H)
32-pin SOP (Package Code Q)
32-pin TSOP (TYPE II) (Package Code T2)
A11 1
A9 2
A8 3
A13 4
WE 5
A18 6
A15 7
VDD 8
A17 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
32 OE
31 A10
30 CS1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
A17 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
32 VDD
31 A15
30 A18
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  A
02/09/2012
3


3Pages


IS62WV5128DALL 電子部品, 半導体
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol Parameter
Test Conditions
Min.
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –1 mA
2.4
Vol
Output LOW Voltage
Vdd = Min., Iol = 2.1 mA
Vih
Input HIGH Voltage
2
Vil
Input LOW Voltage(1)
–0.3
Ili
Ilo
Input Leakage
Output Leakage
GND Vin Vdd
GND Vout Vdd, Outputs Disabled
–1
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.3V-3.6V
Symbol Parameter
Test Conditions
Min.
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –1.0 mA
1.8
Vol
Output LOW Voltage
Vdd = Min., Iol = 2.1 mA
Vih
Input HIGH Voltage
2.0
Vil
Input LOW Voltage(1)
–0.3
Ili
Input Leakage
GND Vin Vdd
–1
Ilo
Output Leakage
GND Vout Vdd, Outputs Disabled
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol Parameter
Test Conditions
Vdd
Min.
Voh
Output HIGH Voltage
Ioh = -0.1 mA
1.65-2.2V
1.4
Vol
Output LOW Voltage
Iol = 0.1 mA
1.65-2.2V
Vih
Input HIGH Voltage
1.65-2.2V
1.4
Vil(1)
Input LOW Voltage
1.65-2.2V
–0.2
Ili
Input Leakage
GND Vin Vdd
–1
Ilo
Output Leakage
GND Vout Vdd, Outputs Disabled
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
0.2
Vdd + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  A
02/09/2012

6 Page



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部品番号部品説明メーカ
IS62WV5128DALL

ULTRA LOW POWER CMOS STATIC RAM

ISSI
ISSI


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