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IS66WVE4M16BLL の電気的特性と機能

IS66WVE4M16BLLのメーカーはISSIです、この部品の機能は「3.0V Core Async/Page PSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS66WVE4M16BLL
部品説明 3.0V Core Async/Page PSRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS66WVE4M16BLL Datasheet, IS66WVE4M16BLL PDF,ピン配置, 機能
IS66WVE4M16BLL
3.0V Core Async/Page PSRAM
Overview
The IS66WVE4M16BLL is an integrated memory device containing 64Mbit Pseudo Static Random Access
Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several
power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and
Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 70ns
Intrapage Read access : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 180 uA (max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial -40°C~85°C
Packages:
48-ball TFBGA, 48-pin TSOP-I
Notes:
1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM Marketing at [email protected]
for additional information.
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev.A | May 2011
www.issi.com - [email protected]
1

1 Page





IS66WVE4M16BLL pdf, ピン配列
IS66WVE4M16BLL
48Ball TFBGA Ball Assignment
1 23 456
A
LB# OE#
A0
A1 A2 ZZ#
B
DQ8 UB#
A3
A4 CE# DQ0
C
DQ9 DQ10
A5
A6 DQ1 DQ2
D
VSSQ DQ11 A17
A7 DQ3 VDD
E
VDDQ DQ12 A21
A16 DQ4 VSS
F
DQ14 DQ13 A14
A15 DQ5 DQ6
G
DQ15 A19
A12
A13 WE# DQ7
H A18 A8 A9 A10 A11 A20
[Top View]
(Ball Down)
Rev.A | May 2011
www.issi.com - [email protected]
3


3Pages


IS66WVE4M16BLL 電子部品, 半導体
IS66WVE4M16BLL
Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
Mode
Standby
Read
Write
No operation
PAR
DPD
Load
Configuration
register
Power
Standby
Active
Active
Idle
PAR
DPD
Active
CE# WE# OE# UB#/LB# ZZ#
H XX X H
L HL L H
L LX L H
L XX X H
H XX X L
H XX X L
L LX X L
DQ
[15:0]4
High-Z
Data-Out
Data-In
X
High-Z
High-Z
High-Z
Note
2,5
1,4
1,3,4
4,5
6
6
Notes
1. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.
When only LB# is in select mode, DQ0~DQ7 are affected as shown. When only UB# is
in select mode, DQ8~DQ15 are affected as shown.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
inputs/outputs are internally isolated from any external influence.
3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
Rev.A | May 2011
www.issi.com - [email protected]
6

6 Page



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部品番号部品説明メーカ
IS66WVE4M16BLL

3.0V Core Async/Page PSRAM

ISSI
ISSI


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