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PDF PI6C185-00 Data sheet ( Hoja de datos )
| Número de pieza | PI6C185-00 | |
| Descripción | Precision 1-7 Clock Buffer | |
| Fabricantes | Pericom Semiconductor | |
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Precision 1-7 Clock Buffer
Product Features
• High-speed, low-noise non-inverting 1-7 buffer
• Switching speed up to 140 MHz (PI6C185-00A)*
• Supports up to three mobile SDRAM DIMMs
• Low skew (<250ps) between any two output clocks
• I2C Serial Configuration interface
• Multiple VDD, VSS pins for noise reduction
• 3.3V power supply voltage
• 20-pin TSSOP (L) and QSOP (Q) packages
* Maximum Operating Frequencies:
PI6C185-00 = 125 MHz;
PI6C185-00A = 140 MHz.
Block Diagram
Description
The PI6C185-00 is a high-speed low-noise 1-7 non-inverting
buffer designed for SDRAM clock buffer applications.
This buffer is intended to be used with the PI6C10X clock genera-
tor for Intel Architecture-based Mobile systems.
At power up all SDRAM output are enabled and active. The I2C
Serial control may be used to individually activate/deactivate any
of the 7 output drivers.
Note:
Purchase of I2C components from Pericom conveys a license to use
them in an I2C system as defined by Philips.
Pin Configuration
BUF_IN
SDATA
SCLOCK
I2C
I/O
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM6
VDD 1
SDRAM0 2
SDRAM1 3
VSS 4
BUF_IN 5
VDD 6
SDRAM2 7
VSS 8
VDD 9
SDATA 10
20-Pin
L, Q
20 VDD
19 SDRAM6
18 SDRAM5
17 VSS
16 VDD
15 SDRAM4
14 SDRAM3
13 VSS
12 VSS
11 SCLK
1 PS8317A 03/22/01
1 page  
PI6C185-00
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Output
Buffer
Test
Point
Test Load
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKH
tSDKP
tSDRISE
tSDKL
tSDFALL
Input
Waveform
1.5V
tplh
Output
Waveform
1.5V
1.5V
tphl
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock Min. Load Max. Load Units
Notes
SDRAM
20
30
pF
SDRAM DIMM
Specification
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series RS resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
5
PS8317A 03/22/01
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6C185-00.PDF ] | |
Hoja de datos destacado
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