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PDF PI6C185-01B Data sheet ( Hoja de datos )
| Número de pieza | PI6C185-01B | |
| Descripción | Precision 1-5 Clock Buffer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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Precision 1-5 Clock Buffer
Features
High-speed, low-noise non-inverting 1-5 buffer
Switching speed up to 140 MHz
Supports up to two SODIMMs
Low skew (<250ps) between any two output clocks
I2C Serial Configuration interface
Multiple VDD, VSS pins for noise reduction
3.3V power supply voltage
16-pin TSSOP (L) and QSOP (Q) packages
Description
The PI6C185-01B, a high-speed low-noise 1-5 non-inverting buffer
designed for SDRAM clock buffer applications, is intended to be
used with the PI6C10X clock generator for Intel Architecture-based
Mobile systems.
At power up, all SDRAM outputs are enabled and active. The I2C
Serial control may be used to individually activate/deactivate any
of the five output drivers.
Note:
Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.
Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
Pin Configuration
Vdd 1
16 Vdd
SDRAM0 2
15 SDRAM4
SDRAM1 3
14 Vss
Vss 4
16-Pin
L, Q
13
Vdd
BUF_IN 5
12 SDRAM3
Vdd 6
11 SDRAM2
SDATA 7
10 Vss
SCLK 8
9 Vss
SDATA
SCLOCK
I2C
I/O
1 PS8466 05/03/00
1 page  
PI6C185-01B
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Output
Buffer
Test
Point
Test Load
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKH
tSDKP
tSDRISE
tSDFALL
tSDKL
Input
Waveform
1.5V
tplh
Output
Waveform
1.5V
1.5V
tphl
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock Min Load Max Load Units
Notes
SDRAM
15
20 pF SDRAM DIMM Specification
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place R series resistors and CI capacitors as close as possible to the respective clock pins. Typical
S
value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise
and fall time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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5 PS8466 05/03/00
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PI6C185-01B.PDF ] | |
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