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PI6C185-02B の電気的特性と機能

PI6C185-02BのメーカーはPericom Semiconductorです、この部品の機能は「Precision 1-7 Clock Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 PI6C185-02B
部品説明 Precision 1-7 Clock Buffer
メーカ Pericom Semiconductor
ロゴ Pericom Semiconductor ロゴ 




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PI6C185-02B Datasheet, PI6C185-02B PDF,ピン配置, 機能
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Precision 1-7 Clock Buffer
Features
• High speed: 140 MHz
• Low noise non-inverting 1-7 buffer
• Supports up to three SDRAM DIMMs
• Low skew (<250ps) between any two output clocks
• I2C Serial Configuration interface
• Multiple Vdd, Vss pins for noise reduction
• 3.3V power supply voltage
• 16-pin TSSOP (L) and QSOP (Q) packages
Description
The PI6C185-02B, a high-speed low-noise 1-7 non-inverting
buffer, is designed for SDRAM clock buffer applications. It is
intended to be used with the PI6C10X clock generator for Intel
Architecture-based Mobile systems.
At power up, all SDRAM outputs are enabled and active. The I2C
Serial control may be used to individually activate/deactivate any
of the seven output drivers.
Note:
Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.
Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
Pin Configuration
Vdd 1
16 SDRAM6
SDRAM0 2
15 SDRAM5
SDRAM1
3
14
16-Pin
Vss
Vss 4 L,Q 13 Vdd
BUF_IN 5
12 SDRAM4
SDRAM2 6
11 SDRAM3
Vdd 7
10 Vss
SDATA 8
9 SCLK
SDRAM6
SDATA
SCLOCK
I2C
I/O
1 PS8469 05/03/00

1 Page





PI6C185-02B pdf, ピン配列
PI6C185-02B
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899P0011r22e3344c55i66s77i88o9900n1122133-445576677C8899l00o11c2211k2233B4455u6677f88f99e0011r22
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C185-02B, a slave receiver device, cannot be read back.
Sub addressing is not supported. To change one of the control
bytes, all preceding bytes must be sent.
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving
device.
During normal data transfers, SDATA changes only when SCLK is
LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLK is HIGH indicates a “start” condition; a LOW to HIGH
transition on SDATA while SCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW = write to addressed device). If the device’s
own address is detected, PI6C185-02B generates an acknowledge
by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condition
is detected.
1
2
3
Following acknowledgement of the address byte (0D2H), two more
bytes must be sent:
1. “Command Code” byte &2. “Byte Count” byte.
4
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
5
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... –65°C to +150°C
Ambient Temperature with Power Applied ....... –0°C to +70°C
3.3V Supply Voltage to Ground Potential ....... –0.5V to +4.6V
DC Input Voltage ............................................. –0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Supply Current (VDD = +3.465V, Cload = max)
6
7
8
Symbol
Parameter
Test Condition
Min. Typ. Max. Units
9
IDD Supply Current BUF_IN = 0 MHz
IDD Supply Current BUF_IN = 66.66 MHz
IDD Supply Current BUF_IN = 100.0 MHz
3
mA
TBD
10
11
12
13
14
15
PS8469 05/03/00
3


3Pages


PI6C185-02B 電子部品, 半導体
PI6C185-02B
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678P90r1e23c4i5s6i7o89n01123-47567C89l0o1c21k23B45u67f8f9e01r2
PI6C185-02B
100/66 MHz
Clock from
Chipset
SDRAM 7 RS
SDRAM
DIMM
CL Spec.
Figure 2. Design Guidelines
16-Pin TSSOP (L) Package
16
.169 4.3
.177 4.5
1
.193
.201
4.9
5.1
.0256
BSC
0.65
.007
.012
0.19
0.30
.047
max.
1.20
SEATING
PLANE
.002 0.05
.006 0.15
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
0.45 .018
0.75 .030
.252
BSC
6.4
.004 0.09
.008 0.20
Ordering Information
P/N
PI6C185-02BL
PI6C185-02BQ
Description
TSSOP Package
QSOP Package
16-Pin QSOP (Q) Package
16
.150 3.81
.157 3.99
1
.189
.197
4.80
5.00
.008
0.203 REF
.053 1.35
.069 1.75
.025
BSC
0.635
.008
.012
0.203
0.305
SEATING
PLANE
.004 0.101
.010 0.254
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
.015 x 45° 0.38
0.41 .016
1.27 .050
.228
.244
5.79
6.19
.007 0.178
.010 0.254
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
6 PS8469 05/03/00

6 Page



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部品番号部品説明メーカ
PI6C185-02B

Precision 1-7 Clock Buffer

Pericom Semiconductor
Pericom Semiconductor


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