IDT54FCT377DT Datasheet PDF - Integrated Device Tech
| Part Number | IDT54FCT377DT | |
| Description | FAST CMOS OCTAL D FLIP-FLOP | |
| Manufacturers | Integrated Device Tech | |
| Logo |  |
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Integrated Device Technology, Inc.
FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
IDT54/74FCT377T/AT/CT/DT
FEATURES:
• Std., A, C and D speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Power off disable outputs permit “live insertion”
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW. The register is fully
edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop’s O output. The CE input must be
stable only one set-up time prior to the LOW-to-HIGH transi-
tion for predictable operation.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CE
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
CP
O0 O1 O2 O3 O4 O5 O6 O7
2630 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
6.14
APRIL 1995
DSC-4200/3
1
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IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT377T
Symbol
Parameter
tPLH Propagation Delay
tPHL CP to On
tSU Set-Up Time HIGH or LOW
Dn to CP
tH Hold Time HIGH or LOW
Dn to CP
tSU Set-Up Time HIGH or LOW
CE to CP
tH Hold Time HIGH or LOW
CE to CP
tW Clock Pulse Width,
HIGH or LOW
Condition(1)
CL = 50pF
RL = 500Ω
Com'l.
Min.(2)
2.0
Max.
13.0
Mil.
Min.(2)
2.0
Max.
15.0
2.5 — 3.0 —
2.0 — 2.5 —
4.0 — 4.0 —
1.5 — 1.5 —
7.0 — 7.0 —
FCT54/74FCT377AT
Com'l.
Min.(2)
2.0
Max.
7.2
Mil.
Min.(2)
2.0
Max.
8.3
Unit
ns
2.0 — 2.0 — ns
1.5 — 1.5 — ns
3.5 — 3.5 — ns
1.5 — 1.5 — ns
6.0 — 7.0 — ns
2630 tbl 06
IDT54/74FCT377CT
Com'l.
Symbol
Parameter
Condition(1)
Min.(2)
tPLH Propagation Delay
tPHL CP to On
CL = 50pF
RL = 500Ω
2.0
tSU Set-Up Time HIGH or LOW
2.0
Dn to CP
tH Hold Time HIGH or LOW
1.5
Dn to CP
tSU Set-Up Time HIGH or LOW
CE to CP
3.5
tH Hold Time HIGH or LOW
CE to CP
1.5
tW Clock Pulse Width,
6.0
HIGH or LOW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Max.
5.2
—
—
—
—
—
Mil.
Min.(2)
2.0
Max.
5.5
2.0 —
1.5 —
3.5 —
1.5 —
7.0 —
FCT54/74FCT377DT
Com'l.
Min.(2)
2.0
Max.
4.4
Mil.
Min.(2)
—
Max.
—
Unit
ns
2.0 — — — ns
1.0 — — — ns
3.0 — — — ns
0.0 — — — ns
3.0 — — — ns
2630 tbl 07
6.14 5
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