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IDT74FCT377T の電気的特性と機能

IDT74FCT377TのメーカーはIntegrated Device Techです、この部品の機能は「FAST CMOS OCTAL D FLIP-FLOP」です。


製品の詳細 ( Datasheet PDF )

部品番号 IDT74FCT377T
部品説明 FAST CMOS OCTAL D FLIP-FLOP
メーカ Integrated Device Tech
ロゴ Integrated Device Tech ロゴ 




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IDT74FCT377T Datasheet, IDT74FCT377T PDF,ピン配置, 機能
Integrated Device Technology, Inc.
FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
IDT54/74FCT377T/AT/CT/DT
FEATURES:
• Std., A, C and D speed grades
• Low input and output leakage 1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Power off disable outputs permit “live insertion”
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW. The register is fully
edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop’s O output. The CE input must be
stable only one set-up time prior to the LOW-to-HIGH transi-
tion for predictable operation.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CE
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
CP
O0 O1 O2 O3 O4 O5 O6 O7
2630 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
6.14
APRIL 1995
DSC-4200/3
1

1 Page





IDT74FCT377T pdf, ピン配列
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2)
Max.
VIH Input HIGH Level
Guaranteed Logic HIGH Level
2.0 —
VIL Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
IIL
Input LOW Current(4)
VCC = Max.
VI = 0.5V
II
Input HIGH Current(4)
VCC = Max., VI = VCC (Max.)
— — 0.8
——
±1
——
±1
——
±1
VIK Clamp Diode Voltage VCC = Min., IN = –18mA
IOS Short Circuit Current
VCC = Max.(3), VO = GND
— –0.7 –1.2
–60 –120 –225
VOH Output HIGH Voltage
VCC = Min.
IOH = –6mA MIL.
2.4 3.3
VIN = VIH or VIL
IOH = –8mA COM’L.
IOH = –12mA MIL.
2.0 3.0
IOH = –15mA COM’L.
VOL Output LOW Voltage
VCC = Min.
IOL = 32mA MIL.
— 0.3 0.5
VIN = VIH or VIL
IOL = 48mA COM’L.
IOFF
Input/Output Power Off
VCC = 0V, VIN or VO 4.5V
Leakage(5)
——
±1
VH Input Hysteresis
— 200
ICC Quiescent Power
VCC = Max.
— 0.01
1
Supply Current
VIN = GND or VCC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = -55°C.
5. This parameter is guaranted but not tested.
Unit
V
V
µA
µA
µA
V
mA
V
V
V
µA
mV
mA
2630 tbl 05
6.14 3


3Pages


IDT74FCT377T 電子部品, 半導体
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
VIN
Pulse
Generator
D.U.T.
RT
VOUT
50pF
CL
500
500
7.0V
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
2630 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2630 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tSU
tSU
tH
tREM
tH
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2630 drw 05
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
1.5V
tW
1.5V
2630 drw 06
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
2630 drw 07
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
DISABLE
tPLZ
3.5V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
NOTES:
2630 drw 08
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
6.14 6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IDT74FCT377

FAST CMOS OCTAL D FLIP-FLOP

Integrated Device Tech
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IDT74FCT377A

FAST CMOS OCTAL D FLIP-FLOP

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IDT74FCT377AT

FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

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IDT74FCT377C

FAST CMOS OCTAL D FLIP-FLOP

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