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IDT74FCT377A の電気的特性と機能

IDT74FCT377AのメーカーはIntegrated Device Techです、この部品の機能は「FAST CMOS OCTAL D FLIP-FLOP」です。


製品の詳細 ( Datasheet PDF )

部品番号 IDT74FCT377A
部品説明 FAST CMOS OCTAL D FLIP-FLOP
メーカ Integrated Device Tech
ロゴ Integrated Device Tech ロゴ 




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IDT74FCT377A Datasheet, IDT74FCT377A PDF,ピン配置, 機能
®
Integrated Device Technology, Inc.
FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
IDT54/74FCT377
IDT54/74FCT377A
IDT54/74FCT377C
FEATURES:
• IDT54/74FCT377 equivalent to FASTspeed
IDT54/74FCT377A 25% faster than FAST
IDT54/74FCT377C 40% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• IIH and IIL only 5µA max.
• CMOS power levels (1mW typ. static)
• CMOS output level compatible
• Meets or exceeds JEDEC Standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT377/A/C is an octal D flip-flop built using
an advanced dual metal CMOS technology. The IDT54/
74FCT377/A/C have eight edge-triggered, D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously when the
Clock Enable (CE) is LOW. The register is fully edge-
triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the corre-
sponding flip-flop’s O output. The CE input must be stable only
one set-up time prior to the LOW-to-HIGH clock transition for
predictable operation.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CE
DQ
CP
DQ
CP
CP
O0
PIN CONFIGURATIONS
O1
DQ
CP
O2
DQ
CP
O3
CE
O0
D0
D1
O1
O2
D2
D3
O3
GND
1 20
2 19
3 18
4 P20-1 17
5
D20-1
SO20-2
16
6 & 15
7 E20-1 14
8 13
9 12
10 11
Vcc
O7
D7
D6
O6
O5
D5
D4
O4
CP
DIP/SOIC/CERPACK
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.14
DQ
CP
DQ
CP
DQ
CP
DQ
CP
O4 O5 O6 O7
2535 drw 02
INDEX
32
20 19
D1 4
1 18 D7
O1 5
17 D6
O2 6 L20-2 16 O6
D2 7
15 O5
D3 8
14 D5
9 10 11 12 13
2535 drw 01
LCC
TOP VIEW
MAY 1992
DSC4606/2
1

1 Page





IDT74FCT377A pdf, ピン配列
IDT54/74FCT377/A/C
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2)
Max.
VIH Input HIGH Level
Guaranteed Logic HIGH Level
2.0 — —
VIL Input LOW Level
Guaranteed Logic LOW Level
— — 0.8
IIH Input HIGH Current VCC = Max.
IIL Input LOW Current
VI =VCC
VI = 2.7V
VI = 0.5V
— —5
— — 5(4)
— — –5(4)
VI = GND
— — –5
VIK
Clamp Diode Voltage
VCC = Min., IN = –18mA
IOS
Short Circuit Current
VCC = Max.(3), VO = GND
— –0.7 –1.2
–60
–120
VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VHC
VCC
VCC = Min.
IOH = –300µA
VHC
VCC
VIN = VIH or VIL
IOH = –12mA MIL.
2.4
4.3 —
IOH = –15mA COM’L. 2.4
4.3 —
VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VCC = Min.
IOL = 300µA
— GND VLC
— GND VLC(4)
VIN = VIH or VIL
IOL = 32mA MIL.
— 0.3 0.5
IOL = 48mA COM’L.
0.3 0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
Unit
V
V
µA
V
mA
V
V
2535 tbl 05
7.14 3


3Pages


IDT74FCT377A 電子部品, 半導体
IDT54/74FCT377/A/C
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC 7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500
50pF
RT
500
CL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
2535 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t SU
t SU
tH
t REM
tH
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
1.5V
tW
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
t PLH
t PHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
DISABLE
tPLZ
3V
1.5V
0V
3.5V
tPHZ
0.3V V OL
0.3V V OH
0V
NOTES
2535 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns;
tR 2.5ns.
7.14 6

6 Page



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共有リンク

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部品番号部品説明メーカ
IDT74FCT377

FAST CMOS OCTAL D FLIP-FLOP

Integrated Device Tech
Integrated Device Tech
IDT74FCT377A

FAST CMOS OCTAL D FLIP-FLOP

Integrated Device Tech
Integrated Device Tech
IDT74FCT377AT

FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

Integrated Device Tech
Integrated Device Tech
IDT74FCT377C

FAST CMOS OCTAL D FLIP-FLOP

Integrated Device Tech
Integrated Device Tech


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