DataSheet.jp

MAX9361 の電気的特性と機能

MAX9361のメーカーはMaxim Integratedです、この部品の機能は「LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators」です。


製品の詳細 ( Datasheet PDF )

部品番号 MAX9361
部品説明 LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators
メーカ Maxim Integrated
ロゴ Maxim Integrated ロゴ 




このページの下部にプレビューとMAX9361ダウンロード(pdfファイル)リンクがあります。

Total 8 pages

No Preview Available !

MAX9361 Datasheet, MAX9361 PDF,ピン配置, 機能
19-2327; Rev 2; 12/08
EVAALVUAAILTAIOBNLEKIT
LVTTL/TTL/CMOS-to-Differential LVECL/
ECL Translators
General Description
The MAX9360/MAX9361 are low-skew, single LVTTL/
TTL/CMOS-to-differential LVECL/ECL translators
designed for high-speed signal and clock driver appli-
cations. For interfacing to LVTTL/TTL/CMOS input sig-
nals, these devices operate over a 3.0V to 5.5V supply
range, allowing high-performance clock or data distrib-
ution. For interfacing to differential LVECL/ECL output
signals, these devices operate from a -2.375V to -5.5V
supply.
The MAX9360 is a 3.3V LVTTL/CMOS-to-LVECL/ECL
translator that operates at a typical speed of 3GHz. The
MAX9361 is a 5V TTL/CMOS-to-LVECL/ECL translator
that operates at a typical speed of 1.3GHz. Both
devices can be used to drive either LVECL devices or
standard ECL devices with a negative supply range of
-2.375V to -5.5V.
The devices default to high if the input is disconnected,
and feature ultra-low propagation delay: 440ps for the
MAX9360, 810ps for the MAX9361.
Applications
Clock/Data-Level Translation
Features
o Output High with Input Open
o -2.375V to -5.5V LVECL/ECL Operation
o ESD Protection > 2kV (Human Body Model)
o 3.0V to 3.6V LVTTL/CMOS Operation (MAX9360)
Improved Second Source of the MC100EPT24
Low 13.8mA (typ) IEE Supply Current
440ps (typ) Propagation Delay
> 300mV Output at 1GHz
o 4.5V to 5.5V TTL Operation (MAX9361)
Improved Second Source of the MC100ELT24
Low 6.6mA (typ) IEE Supply Current
600ps (typ) Propagation Delay
> 300mV Output at 250MHz
Ordering Information
PART
MAX9360EKA-T
MAX9360ESA
MAX9361EKA-T
MAX9361ESA
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
8 SOT23
8 SO
8 SOT23
8 SO
TOP
MARK
AAJI
AAJJ
TOP VIEW
D1
VEE 2
N.C. 3
8 GND
7Q
6Q
N.C. 4
MAX9360/
MAX9361
SOT23
5 VCC
Pin Configurations
VEE 1
D2
8 VCC
7Q
N.C. 3
6Q
N.C. 4
MAX9360/
MAX9361
SO
5 GND
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 Page





MAX9361 pdf, ピン配列
LVTTL/TTL/CMOS-to-Differential LVECL/
ECL Translators
DC ELECTRICAL CHARACTERISTICS—MAX9361
(VCC = 4.5V to 5.5V, VEE = -2.375V to -5.5V, VGND = 0, outputs terminated with 50Ω ±1% to -2.0V. Typical values are at VCC = 5V,
VIH = 2.0V, VIL = 0.8V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS
TTL INPUT (D)
Input High Current
IIH
Input Low Current
Input Clamp
Voltage
IIL
VIK
Input High Voltage
VIH
Input Low Voltage
VIL
LVECL/ECL OUTPUTS (Q, Q)
Output High
Voltage
VOH
Output Low Voltage VOL
Differential Output
Swing (VOH - VOL)
VOH -
VOL
POWER SUPPLY
Power-Supply
Current
ICC
Internal Chip
Current
IEE
VIN = 2.7V
VIN = VCC
VIN = 0.5V
IIN = -18mA
(Note 4)
(Note 4)
-40°C (SO)
MIN TYP MAX
+25°C
MIN TYP MAX
+85°C
UNITS
MIN TYP MAX
-30 +30 -30 +30 -30 +30
-10 +10 -10 +10 -10 +10
-200 -55
-200 -61
-200 -71
-1.2 -1.2 -1.2
2.0 2.0 2.0
0.8 0.8 0.8
µA
µA
V
V
V
-1.055
-0.880 -1.055
-0.880 -1.025
-0.880 V
-1.875
-1.555 -1.810
-1.605 -1.810
-1.605 V
550 699
550 691
550 677
mV
3.0 7.0
9 20
3.5 7.0
10 20
4.3 7.0 mA
11 20 mA
_______________________________________________________________________________________ 3


3Pages


MAX9361 電子部品, 半導体
LVTTL/TTL/CMOS-to-Differential LVECL/
ECL Translators
PIN
SO SOT23
12
21
3, 4 3, 4
58
67
76
85
Pin Description
NAME
FUNCTION
VEE
D
N.C.
GND
Q
Q
VCC
Negative Supply Voltage. Bypass VEE to GND with 0.1µF and 0.01µF ceramic capacitors.
Place the capacitors as close as possible to the device with the smaller value capacitor
closest to the device.
LVTTL/CMOS Input for MAX9360. TTL/CMOS input for MAX9361.
No Connect. Connect to GND.
Ground
Inverting Differential LVECL/ECL Output. Typically terminate with 50Ω resistor to -2V.
Noninverting Differential LVECL/ECL Output. Typically terminate with 50Ω resistor to -2V.
Positive Supply Voltage. Bypass VCC to GND with 0.1µF and 0.01µF ceramic capacitors.
Place the capacitors as close as possible to the device with the smaller value capacitor
closest to the device.
50%
D
Q
SINGLE-ENDED WAVEFORMS
Q
tPLH
VOH - VOL
80% VOH - VOL
DIFFERENTIAL WAVEFORM
Q-Q
20%
tR
VOH - VOL
Figure 1. Input-to-Output Propagation Delay and Transition Timing Diagram
50%
tPHL
VIH
VIL
VOH
VOL
80%
0 (DIFFERENTIAL)
20%
tF
6 _______________________________________________________________________________________

6 Page



ページ 合計 : 8 ページ
 
PDF
ダウンロード
[ MAX9361 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
MAX9360

LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators

Maxim Integrated
Maxim Integrated
MAX9360EKA-T

LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators

Maxim Integrated
Maxim Integrated
MAX9360ESA

LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators

Maxim Integrated
Maxim Integrated
MAX9361

LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators

Maxim Integrated
Maxim Integrated


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap