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SKY13551-668LF の電気的特性と機能

SKY13551-668LFのメーカーはSkyworks Solutionsです、この部品の機能は「DP10T Main/Receive Diversity Switch」です。


製品の詳細 ( Datasheet PDF )

部品番号 SKY13551-668LF
部品説明 DP10T Main/Receive Diversity Switch
メーカ Skyworks Solutions
ロゴ Skyworks Solutions ロゴ 




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SKY13551-668LF Datasheet, SKY13551-668LF PDF,ピン配置, 機能
DATA SHEET
SKY13551-668LF: 0.4 to 3.8 GHz DP10T (SP5T/SP5T)
Main/Receive Diversity Switch with MIPI RFFE Interface for
Carrier Aggregation
Applications
3G/4G multimode cellular handsets (UMTS, CDMA2000, LTE)
Carrier aggregation diversity
Features
Broadband frequency range: 0.4 to 3.8 GHz
Single, positive DC power supply (2.5 to 4.8 V)
Integrated, programmable MIPI interface using separate
registers for ANT_A and ANT_B
Dual antenna ports can be connected externally to a diplexer
Small QFN (16-pin, 1.6 x 2.4 x 0.55 mm) package
(MSL1, 260 C per JEDEC J-STD-020)
Skyworks GreenTM products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Definition of GreenTM, document number
SQ04–0074.
TRXA1
TRXA2
TRXA3
TRXA4
TRXA5
TRXB1
TRXB2
TRXB3
TRXB4
TRXB5
ANT_A
ANT_B
Bias Logic Block
Description
The SKY13551-668LF is a dual single-pole, five-throw (2xSP5T)
Mobile Industry Processor Interface (MIPI) controlled antenna
switch designed specifically for receive diversity in carrier
aggregation applications.
The 2xSP5T switch is optimized for broadband performance.
Using advanced switching technologies, the SKY13551-668LF
maintains low insertion loss and high isolation for all switching
paths. The high-linearity performance and low insertion loss
achieved by the SKY13551-668LF makes it an ideal choice for
carrier aggregation applications in both main and diversity
antenna switching. The switch also exhibits excellent
second/third order intermodulation distortion (IMD2/IMD3)
performance.
Figure 1. SKY13551-668LF Block Diagram
Switching is controlled by an integrated MIPI decoder. The two
switches can be configured independently. There are separate
registers for each SP5T switch. No external DC blocking
capacitors are required on the RF paths as long as no DC voltage
is applied to those paths.
The SKY13551-668LF is manufactured in a compact,
1.6 x 2.4 x 0.55 mm, 16-pin surface-mount Quad Flat No-Lead
(QFN) package.
A functional block diagram is shown in Figure 1. The pin
configuration and package are shown in Figure 2. Signal pin
assignments and functional pin descriptions are provided in
Table 1.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
203267D • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • January 22, 2016
1

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SKY13551-668LF pdf, ピン配列
DATA SHEET • SKY13551-668LF: MAIN/RECEIVE DIVERSITY SWITCH FOR CARRIER AGGREGATION
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY13551-668LF are
provided in Table 2. Electrical specifications are provided in
Tables 3 and 4.
IMD2 and IMD3 test conditions for various frequencies are listed
in Tables 5 and 6, respectively.
Figure 3 illustrates the test setup used to measure
intermodulation products. This industry standardized test is used
to simulate the WCDMA linearity of the antenna switch. A
+20 dBm continuous wave (CW) signal, fFUND, is sequentially
applied to the TRX ports, while a –15 dBm CW blocker signal,
fBLK, is applied to the ANT port.
The resulting third order intermodulation distortion (IMD3), fRX, is
measured over all phases of fFUND. The SKY13551-668LF exhibits
exceptional performance for all RF ports.
Table 7 describes the register content and programming
read/write sequences. Refer to the MIPI Alliance Specification for
RF Front-End Control Interface (RFFE), v1.10 (26 July 2011) for
additional information on MIPI programming sequences and MIPI
bus specifications.
Figure 4 provides the timing diagram for register write
commands. Figure 5 provides the timing diagram for register read
commands.
Register descriptions and programming information is provided in
Table 8. Tables 9 and 10 provide the Register_0 and Register_1
logic, respectively.
Table 2. SKY13551-668LF Absolute Maximum Ratings1
Parameter
Symbol
Minimum
Maximum
Units
Supply voltage
VDD
2.5 5.0
V
Digital control signal
VIO
2V
SCLK port voltage
VSCLK
VIO V
SDATA port voltage
VSDATA
VIO V
LTE input power
PIN +31 dBm
Storage temperature
TSTG
–55 +150
C
Operating temperature
TOP
–30 +90
C
1 Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set
at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION: Although this device is designed to be as robust as possible, electrostatic discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
203267D • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • January 22, 2016
3


3Pages


SKY13551-668LF 電子部品, 半導体
DATA SHEET • SKY13551-668LF: MAIN/RECEIVE DIVERSITY SWITCH FOR CARRIER AGGREGATION
Signal Generator
fFUND = 1950 MHz,
+20 dBm
Circulator
Coupler to Monitor
Input Power
fBLK
1760 MHz,
–15 dBm
fFUND
1950 MHz,
+20 dBm
fRX
2140 MHz,
Measure Tone
1950 MHz
Bandpass Filter
Duplexer
Phase Shifter
Skyworks Switch
fFUND = +20 dBm
fBLK = –15 dBm
Circulator
1760 MHz
Bandpass Filter
Signal Generator
fBLK = 1760 MHz,
–15 dBm
Spectrum Analyzer
fRX = 2140 MHz
203267D-003
Figure 3. Typical Third Order Intermodulation Test Setup
Table 7. Command Sequence Bit Definitions
Type SSC C11-C8
Reg_0
Write,
Short
Command
Y
SA[3:0]
Reg_0
Write,
Long
Command
Y
SA[3:0]
Reg_1
Write
Y SA[3:0]
Reg Y SA[3:0]
Read
Legend:
SSC = Sequence start command
C = Command frame bits
C7 C6-C5 C4
1b Data[6:5] Data[4]
0 10b Addr[4]
0 10b Addr[4]
0 11b Addr[4]
DA = Data/address frame bits
BPC = Bus park cycle
Parity
DA7(1)-
C3-C0 Bits BPC DA0(1)
Data{3:0] Y
Y
Addr[3:0] Y
– Data[7:0]
Addr[3:0] Y
Addr[3:0] Y
– Data[7:0]
Y Data[7:0]
BC = Byte count (# of consecutive addresses)
Extended Operation
Parity
DA7(n)-
Bits BPC DA0(n)
––
––
––
––
Parity
Bits
Y
Y
Y
BPC
Y
Y
Y
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
6 January 22, 2016 • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • 203267D

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部品番号部品説明メーカ
SKY13551-668LF

DP10T Main/Receive Diversity Switch

Skyworks Solutions
Skyworks Solutions


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