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C8051F368のメーカーはSilicon Laboratoriesです、この部品の機能は「Mixed Signal ISP Flash MCU Family」です。 |
部品番号 | C8051F368 |
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部品説明 | Mixed Signal ISP Flash MCU Family | ||
メーカ | Silicon Laboratories | ||
ロゴ | |||
このページの下部にプレビューとC8051F368ダウンロード(pdfファイル)リンクがあります。 Total 30 pages
C8051F360/1/2/3/4/5/6/7/8/9
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 10-Bit ADC (‘F360/1/2/6/7/8/9 only)
• Up to 200 ksps
• Up to 21 external single-ended or differential inputs
• VREF from internal VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- 10-Bit Current Output DAC
(‘F360/1/2/6/7/8/9 only)
- Two Comparators
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current (TBD µA)
- Brown-out detector and POR Circuitry
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage
- Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
(See Table 3.1)
- Power saving suspend and shutdown modes
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- 100 MIPS or 50 MIPS throughput with on-chip PLL
- Expanded interrupt handler
- 2-cycle 16 x 16 MAC engine
Memory
- 1280 bytes internal data RAM (256 + 1024)
- 32 kB (‘F360/1/2/3/4/5/6/7) or 16 kB (‘F368/9) Flash;
In-system programmable in 1024-byte Sectors—
1024 bytes are reserved in the 32 kB devices
Digital Peripherals
- up to 39 Port I/O; All 5 V tolerant with high sink cur-
rent
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with six
capture/compare modules
- Real time clock mode using PCA or timer and exter-
nal clock source
- External Memory Interface (EMIF)
Clock Sources
- Two internal oscillators:
• 24.5 MHz with ±2% accuracy supports crystal-less
UART operation
• 80/40/20/10 kHz low frequency, low power
- Flexible PLL technology
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
- 48-pin TQFP (C8051F360/3)
- 32-pin LQFP (C8051F361/4/6/8)
- 28-pin QFN (C8051F362/5/7/9)
Temperature Range: –40 to +85 °C (See
Table 3.1)
ANALOG
PERIPHERALS
VOLTAGE
+
+
COMPARATORS
-
-
A 10-bit
M
U
200 ksps
X ADC
‘F360/1/2/6/7/8/9 only
TEMP
SENSOR
10-bit
Current
DAC
DIGITAL I/O
UART
SMBus
Port 0
SPI
PCA
Port 1
Timer 0
Timer 1
Port 2
Timer 2
Timer 3
Port 3
Port 3
48-pin only
Port 4
HIGH-SPEED CONTROLLER CORE
WDT
16 x 16
MAC
8051 CPU
(100 or 50 MIPS)
1024 B
SRAM
POR
FLEXIBLE
DEBUG Internal Oscillator / 32/16 KB
INTERRUPTS CIRCUITRY
LFO / PLL
ISP FLASH
Rev. 0.2 1/07
Copyright © 2007 by Silicon Laboratories
C8051F36x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
1 Page C8051F360/1/2/3/4/5/6/7/8/9
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 23
1.1.1. Fully 8051 Compatible.............................................................................. 23
1.1.2. Improved Throughput ............................................................................... 23
1.1.3. Additional Features .................................................................................. 24
1.2. On-Chip Memory............................................................................................... 25
1.3. On-Chip Debug Circuitry................................................................................... 25
1.4. Programmable Digital I/O and Crossbar ........................................................... 26
1.5. Serial Ports ....................................................................................................... 27
1.6. Programmable Counter Array ........................................................................... 27
1.7. 10-Bit Analog to Digital Converter..................................................................... 28
1.8. Comparators ..................................................................................................... 29
1.9. 10-bit Current Output DAC................................................................................ 31
2. Absolute Maximum Ratings .................................................................................. 33
3. Global Electrical Characteristics .......................................................................... 34
4. Pinout and Package Definitions............................................................................ 37
5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9)........................................................... 49
5.1. Analog Multiplexer ............................................................................................ 50
5.2. Temperature Sensor ......................................................................................... 51
5.3. Modes of Operation .......................................................................................... 53
5.3.1. Starting a Conversion............................................................................... 53
5.3.2. Tracking Modes........................................................................................ 54
5.3.3. Settling Time Requirements ..................................................................... 55
5.4. Programmable Window Detector ...................................................................... 60
5.4.1. Window Detector In Single-Ended Mode ................................................. 62
5.4.2. Window Detector In Differential Mode...................................................... 63
6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) .................................... 65
6.1. IDA0 Output Scheduling ................................................................................... 65
6.1.1. Update Output On-Demand ..................................................................... 65
6.1.2. Update Output Based on Timer Overflow ................................................ 66
6.1.3. Update Output Based on CNVSTR Edge................................................. 66
6.2. IDAC Output Mapping....................................................................................... 66
7. Voltage Reference (C8051F360/1/2/6/7/8/9) .......................................................... 69
8. Comparators ........................................................................................................... 73
9. CIP-51 Microcontroller .......................................................................................... 83
9.1. Performance ..................................................................................................... 83
9.2. Programming and Debugging Support ............................................................. 84
9.3. Instruction Set ................................................................................................... 85
9.3.1. Instruction and CPU Timing ..................................................................... 85
9.3.2. MOVX Instruction and Program Memory ................................................. 85
9.4. Memory Organization........................................................................................ 88
9.4.1. Program Memory...................................................................................... 89
9.4.2. Data Memory............................................................................................ 90
Rev. 0.2
3
3Pages C8051F360/1/2/3/4/5/6/7/8/9
18.3.SMBus Operation ........................................................................................... 210
18.3.1.Arbitration............................................................................................... 211
18.3.2.Clock Low Extension.............................................................................. 211
18.3.3.SCL Low Timeout................................................................................... 211
18.3.4.SCL High (SMBus Free) Timeout .......................................................... 212
18.4.Using the SMBus............................................................................................ 212
18.4.1.SMBus Configuration Register............................................................... 213
18.4.2.SMB0CN Control Register ..................................................................... 216
18.4.3.Data Register ......................................................................................... 219
18.5.SMBus Transfer Modes.................................................................................. 220
18.5.1.Master Transmitter Mode ....................................................................... 220
18.5.2.Master Receiver Mode ........................................................................... 221
18.5.3.Slave Receiver Mode ............................................................................. 222
18.5.4.Slave Transmitter Mode ......................................................................... 223
18.6.SMBus Status Decoding................................................................................. 224
19. UART0.................................................................................................................... 227
19.1.Enhanced Baud Rate Generation................................................................... 228
19.2.Operational Modes ......................................................................................... 229
19.2.1.8-Bit UART ............................................................................................. 229
19.2.2.9-Bit UART ............................................................................................. 230
19.3.Multiprocessor Communications .................................................................... 231
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 237
20.1.Signal Descriptions......................................................................................... 238
20.1.1.Master Out, Slave In (MOSI).................................................................. 238
20.1.2.Master In, Slave Out (MISO).................................................................. 238
20.1.3.Serial Clock (SCK) ................................................................................. 238
20.1.4.Slave Select (NSS) ................................................................................ 238
20.2.SPI0 Master Mode Operation ......................................................................... 239
20.3.SPI0 Slave Mode Operation ........................................................................... 241
20.4.SPI0 Interrupt Sources ................................................................................... 241
20.5.Serial Clock Timing......................................................................................... 242
20.6.SPI Special Function Registers ...................................................................... 244
21. Timers.................................................................................................................... 251
21.1.Timer 0 and Timer 1 ....................................................................................... 252
21.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 252
21.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 253
21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 253
21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 255
21.2.Timer 2 .......................................................................................................... 260
21.2.1.16-bit Timer with Auto-Reload................................................................ 260
21.2.2.8-bit Timers with Auto-Reload................................................................ 261
21.3.Timer 3 .......................................................................................................... 264
21.3.1.16-bit Timer with Auto-Reload................................................................ 264
21.3.2.8-bit Timers with Auto-Reload................................................................ 265
6 Rev. 0.2
6 Page | |||
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部品番号 | 部品説明 | メーカ |
C8051F360 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F361 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F362 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F363 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |