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PDF IS49RL36160 Data sheet ( Hoja de datos )
| Número de pieza | IS49RL36160 | |
| Descripción | RLDRAM 3 | |
| Fabricantes | Integrated Silicon Solution | |
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576Mb: x18, x36 RLDRAM 3
Features
RLDRAM 3
IS49RL18320 – 2 Meg x 18 x 16 Banks
IS49RL36160 – 1 Meg x 36 x 16 Banks
Features
• 1066 MHz DDR operation (2133 Mb/s/ball data
rate)
• 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock
frequency)
• Organization
– 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)
– 16 banks
• 1.2V center-terminated push/pull I/O
• 2.5V VEXT, 1.35V VDD, 1.2V VDDQ I/O
• Reduced cy cle time ( tRC (MIN) = 8 - 12ns)
• SDR addressing
• Programmable READ/WRITE latency (RL/WL) and
burst length
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Free-running differential input data clocks (DKx,
DKx#) and output data clocks (QKx, QKx#)
• On-die DLL generates CK edge-aligned data and
differential output data clock signals
• 64ms refresh (128K refresh per 64ms)
• 168-ball FBGA package
• 40Ω or 60 Ω matched impedance outputs
• Integrated on-die termination (ODT)
• Single or multibank writes
• Extended operating range (200–1066 MHz)
• READ training register
• Multiplexed and non-multiplexed addressing capa-
bilities
• Mirror function
• Output driver and ODT calibration
• JTAG interface (IEEE 1149.1-2001)
Options
• Clock cycle and tRC timing
– 0.93ns and tRC (MIN) = 8ns
(RL3-2133)
– 0.93ns and tRC (MIN) = 10ns
(RL3-2133)
– 1.07ns and tRC (MIN) = 8ns
(RL3-1866)
– 1.07ns and tRC (MIN) = 10ns
(RL3-1866)
– 1.25ns and tRC (MIN) = 10ns
(RL3-1600)
– 1.25ns and tRC (MIN) = 12ns
(RL3-1600)
• Configuration
– 32 Meg x 18
– 16 Meg x 36
• Operating temperature
– Commercial (TC = 0° to +95°C)
– Industrial (TC = –40°C to +95°C)
• Package
– 168-ball FBGA
– 168-ball FBGA (Pb-free)
• Revision
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this
specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any
information, products or services described herein. Customers are advised to obtain the latest version of this device specification
before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives
written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
01/17/2012
1
1 page  
576Mb: x18, x36 RLDRAM 3
Features
List of Figures
Figure 1: 576Mb RLDRAM® 3 Part Numbers ..................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 32 Meg x 18 Functional Block Diagram ............................................................................................. 10
Figure 4: 16 Meg x 36 Functional Block Diagram ............................................................................................. 11
Figure 5: 168-Ball FBGA ................................................................................................................................. 16
Figure 6: Single-Ended Input Signal ............................................................................................................... 23
Figure 7: Overshoot ....................................................................................................................................... 24
Figure 8: Undershoot .................................................................................................................................... 24
Figure 9: VIX for Differential Signals ................................................................................................................ 25
Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 26
Figure 11: Definition of Differential AC Swing and tDVAC ................................................................................ 26
Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 28
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 29
Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 30
Figure 15: Output Driver ................................................................................................................................ 33
Figure 16: DQ Output Signal .......................................................................................................................... 38
Figure 17: Differential Output Signal .............................................................................................................. 39
Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 39
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 40
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 41
Figure 21: Example Temperature Test Point Location ...................................................................................... 49
Figure 22: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) ............................................... 52
Figure 23: Nominal Slew Rate for tIH (Command and Address - Clock) ............................................................ 53
Figure 24: Tangent Line for tIS (Command and Address - Clock) ...................................................................... 54
Figure 25: Tangent Line for tIH (Command and Address - Clock) ..................................................................... 55
Figure 26: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) .......................................................................... 58
Figure 27: Nominal Slew Rate for tDH (DQ - Strobe) ........................................................................................ 59
Figure 28: Tangent Line for tDS (DQ - Strobe) ................................................................................................. 60
Figure 29: Tangent Line for tDH (DQ - Strobe) ................................................................................................ 61
Figure 30: MRS Command Protocol ............................................................................................................... 63
Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 64
Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 67
Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 69
Figure 34: Read Burst Lengths ........................................................................................................................ 71
Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 72
Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 73
Figure 37: WRITE Command ......................................................................................................................... 74
Figure 38: READ Command ........................................................................................................................... 76
Figure 39: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 77
Figure 40: Multibank AUTO REFRESH Command ........................................................................................... 78
Figure 41: Power-Up/Initialization Sequence ................................................................................................. 80
Figure 42: WRITE Burst ................................................................................................................................. 82
Figure 43: Consecutive WRITE Bursts ............................................................................................................. 83
Figure 44: WRITE-to-READ ............................................................................................................................ 83
Figure 45: WRITE - DM Operation .................................................................................................................. 84
Figure 46: Consecutive Quad Bank WRITE Bursts ........................................................................................... 85
Figure 47: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 85
Figure 48: Basic READ Burst .......................................................................................................................... 86
Figure 49: Consecutive READ Bursts (BL = 2) .................................................................................................. 87
Figure 50: Consecutive READ Bursts (BL = 4) .................................................................................................. 87
Integrated Silicon Solution, Inc. — www.issi.com
01/17/2012
5
5 Page 
Functional Block Diagrams
Figure 4: 16 Meg x 36 Functional Block Diagram
ZQ
RZQ
CK
CK#
CS#
REF#
WE#
MF
RESET#
ODT control
Control
logic
Mode register
23
A[18:0]1
23
Address
register
TCK
TMS
TDI
JTAG
Logic and
Boundary
Scan Register
ZQCL, ZQCS
ZQ CAL
ZQ CAL
Bank 15
Bank 14
VDDQ/2
RTT
Refresh
counter
13
13
Row-
address
MUX
13
Bank 0
row-
address
latch
and
decoder
8192
Bank 1
Bank 0
Bank 0
memory
array
(8192 x 32 x 4 x 36)2
SSeEnNsSeEaAmMpPliLfiIeFrIEs RS
8192
I/O gating
Bank
control
16
DQM mask logic
4
logic
16
32
5 Column
decoder
Column-
address
61
8 61 counter/
latch
11
ODT control
CK/CK#
(0 ....35)
ZQ CAL
DLL
36
144
READ n
logic n 36
DQ
latch
36
QK/QK#
generator
READ
Drivers
8
VDDQ/2
144 RTT
11
ODT control
(0...3)
4
WRITE
144
FIFO
and
drivers
36
CLK 36
in
36 RCVRS
VDDQ/2
RTT
QVLD[1:0]
QK0/QK0#, QK1/QK1#
QK2/QK2#, QK3/QK3#
DQ[35:0]
DK0/DK0#, DK1/DK1#
ODT control
2
DM[1:0]
TDO
Notes: 1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 4 = (length of burst) x 2^ (number of column addresses to WRITE FIFO and READ logic).
DRAFT 12/19/2011
11 Page | ||
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| PDF Descargar | [ Datasheet IS49RL36160.PDF ] | |
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