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Número de pieza | IS49NLS18320A | |
Descripción | Separate I/O RLDRAM 2 Memory | |
Fabricantes | Integrated Silicon Solution | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de IS49NLS18320A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! IS49NLS96400A, IS49NLS18320A
576Mb (64Mbx9, 32Mbx18)
Seperate I/O RLDRAM 2 Memory
ADVANCED INFORMATION
SEPTEMBER 2014
FEATURES
533MHz DDR operation (1.067 Gb/s/pin data rate)
38.4Gb/s peak bandwidth (x18 at 533 MHz clock
frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each
32ms)
8 internal banks
Non-multiplexed addresses (address
multiplexing option available)
SRAM-type interface
Programmable READ latency (RL), row cycle
time, and burst sequence length
Balanced READ and WRITE latencies in order
to optimize data bus utilization
Data mask signals (DM) to mask signal of
WRITE data; DM is sampled on both edges of
DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data
and output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C)
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
OPTIONS
Package:
144-ball FBGA (leaded)
144-ball FBGA (lead-free)
Configuration:
64Mx9
32Mx18
Clock Cycle Timing:
Speed Grade
-18
-25E -25 -33 Unit
tRC 15 15 20 20 ns
tCK 1.875 2.5 2.5 3.3 ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for
products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 9/10/2014
1
1 page IS49NLS96400A, IS49NLS18320A
VDD Supply Power supply: Nominally, 1.8V.
VDDQ
VEXT
VSS
VSSQ
Supply DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
Supply Power supply: Nominally, 2.5V.
Supply Ground.
Supply DQ ground: Isolated on the device for improved noise immunity.
VTT Supply Power supply: Isolated termination supply. Nominally, VDDQ/2.
A22
- Reserved for future use: This signal is not connected and can be connected to ground.
DNU
- Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.
NF - No function: These balls can be connected to ground.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 9/10/2014
5
5 Page IS49NLS96400A, IS49NLS18320A
7. CK and CK# input slew rate must be ≥ 2V/ns (≥ 4V/ns if measured differentially).
8. VID is the magnitude of the difference between the input level on CK and input level on CK#.
9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
10. CK and CK# must cross within the region.
11. CK and CK# must meet at least VID(DC) (MIN.) when static and centered around VDDQ/2.
12. Minimum peak-to-peak swing.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 9/10/2014
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet IS49NLS18320A.PDF ] |
Número de pieza | Descripción | Fabricantes |
IS49NLS18320 | Separate I/O RLDRAM 2 Memory | Integrated Silicon Solution |
IS49NLS18320A | Separate I/O RLDRAM 2 Memory | Integrated Silicon Solution |
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