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PDF IS49NLC36160A Data sheet ( Hoja de datos )
| Número de pieza | IS49NLC36160A | |
| Descripción | Common I/O RLDRAM 2 Memory | |
| Fabricantes | Integrated Silicon Solution | |
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IS49NLC96400A, IS49NLC18320A, IS49NLC36160A
576Mb (64Mbx9, 32Mbx18, 18Mbx36)
Common I/O RLDRAM 2 Memory
ADVANCED INFORMATION
SEPTEMBER 2014
FEATURES
533MHz DDR operation (1.067 Gb/s/pin data rate)
38.4Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each 32ms)
8 internal banks
Non-multiplexed addresses (address multiplexing
option available)
SRAM-type interface
Programmable READ latency (RL), row cycle time,
and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask signals (DM) to mask signal of WRITE
data; DM is sampled on both edges of DK.
OPTIONS
Package:
144-ball FBGA (leaded)
144-ball FBGA (lead-free)
Configuration:
64Mx9
32Mx18
16Mx36
Clock Cycle Timing:
Speed Grade
-18
tRC 15
tCK 1.875
-25E
15
2.5
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C )
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
-25 -33 Unit
20 20 ns
2.5 3.3 ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for
products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 9/10/2014
1
1 page  
IS49NLC96400A, IS49NLC18320A, IS49NLC36160A
1.4 Ball Descriptions
Symbol
A0-A21
Type
Input
Description
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a
MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising
edge of CK.
BA0-BA2 Input Bank address inputs: Selects to which internal bank a command is being applied to.
CK, CK#
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS#
Input
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
DQ0-DQ35
I/O
Data input: The DQ signals form the data bus. During READ commands, the data is referenced to both
edges of QK*. During WRITE commands, the data is sampled at both edges of DK.
DK, DK#
Input
Input data clock: DK* and DK*# are the differential input data clocks. All input data is referenced to both
edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For the x36 device, DQ0–DQ17 are
referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18
devices, all DQ* are referenced to DK and DK#. All DK* and DK*# pins must always be supplied to the
device.
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM
DM Input is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to
ground if not used.
TCK
TMS,TDI
WE#,
REF#
VREF
Input
Input
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Input
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the
command to be executed.
Input Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
External impedance (25–60Ω): This signal is used to tune the device outputs to the system data bus
ZQ I/O impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the minimum impedance mode.
QKX, QKX#
Output
Output data clocks: QK* and QK*# are opposite polarity, output data clocks. They are free running, and
during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of
phase with QK*. For the x36 device, QK0 and QK0# are aligned with DQ0-DQ17, and QK1 and QK1# are
aligned with DQ18-DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0-DQ8, while QK1 and
QK1# are aligned with Q9-Q17. For the x9 device, all DQs are aligned with QK0 and QK0#.
QVLD
Output Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.
TDO
Output
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not
used.
VDD Supply Power supply: Nominally, 1.8V.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 9/10/2014
5
5 Page 
IS49NLC96400A, IS49NLC18320A, IS49NLC36160A
Notes:
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the command, address,
and data signals.
2. Outputs measured with equivalent load:
VTT
50 Ω
DQ Test Point
10 pF
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
4. AC timing may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the
input signals used to test the device is 2 V/ns in the range between VIL(AC) and VIH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. For a x36 device, DQ0-DQ17 is referenced to tQKQ0 and DQ18-DQ35 is referenced to tQKQ1. For a x18 device, DQ0-DQ8 is referenced to tQKQ0 and
DQ9-DQ17 is referenced to tQKQ1. For a x9 device, tQKQ0 is referenced to DQ0-DQ8.
8. tQKQ takes into account the skew between any QKx and any Q.
9. To improve efficiency, eight AREF commands (one for each bank) can be posted to the memory on consecutive cycles at periodic intervals of
1.95μs.
2.8 Clock Input Conditions
Differential Input Clock Operating Conditions
Parameter
Clock Input Voltage Level
Clock Input Differential Voltage Level
Clock Input Differential Voltage Level
Clock Input Crossing Point Voltage Level
Symbol
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
Min
-0.3
0.2
0.4
VDDQ/2-
0.15
Max
VDDQ+0.3
VDDQ+0.6
VDDQ+0.6
VDDQ/2+0.15
Units
V
V
V
V
Notes
8
8
9
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 9/10/2014
11
11 Page | ||
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