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IS49NLC18320のメーカーはIntegrated Silicon Solutionです、この部品の機能は「Common I/O RLDRAM 2 Memory」です。 |
部品番号 | IS49NLC18320 |
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部品説明 | Common I/O RLDRAM 2 Memory | ||
メーカ | Integrated Silicon Solution | ||
ロゴ | |||
このページの下部にプレビューとIS49NLC18320ダウンロード(pdfファイル)リンクがあります。 Total 30 pages
IS49NLC96400,IS49NLC18320,IS49NLC36160
576Mb (x9, x18, x36) Common I/O RLDRAM 2 Memory
FEATURES
ADVANCED INFORMATION
JULY 2012
533MHz DDR operation (1.067 Gb/s/pin data
rate)
38.4Gb/s peak bandwidth (x36 at 533 MHz
clock frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each
32ms)
8 internal banks
Non‐multiplexed addresses (address
multiplexing option available)
SRAM‐type interface
Programmable READ latency (RL), row cycle
time, and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask signals (DM) to mask signal of
WRITE data; DM is sampled on both edges of
DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On‐die DLL generates CK edge‐aligned data and
output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25‐60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On‐die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C; TA = 0°C to +70°C),
Industrial
(TC = ‐40°C to +95°C; TA = ‐40°C to +85°C)
OPTIONS
Package:
144‐ball FBGA (leaded)
144‐ball FBGA (lead‐free)
Configuration:
64Mx9
32Mx18
16Mx36
Clock Cycle Timing:
Speed Grade
‐18
‐25E
‐25 ‐33 ‐5 Unit
tRC 15 15 20 20 20 ns
tCK
1.875
2.5
2.5 3.3 5 ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00E, 06/20/2012
1
1 Page IS49NLC96400,IS49NLC18320,IS49NLC36160
1.2 576Mb (32Mx18) Common I/O BGA Ball‐out (Top View)
1
A VREF
B VDD
C VTT
D A221
E A212
F A5
G A8
H BA2
J NF3
K DK
L REF#
M WE#
N A18
P A15
R VSS
T VTT
U VDD
V VREF
2
VSS
DNU4
DNU4
DNU4
DNU4
DNU4
A6
A9
NF3
DK#
CS#
A16
DNU4
DNU4
QK1
DNU4
DNU4
ZQ
3
VEXT
DQ4
DQ5
DQ6
DQ7
DQ8
A7
VSS
VDD
VDD
VSS
A17
DQ14
DQ15
QK1#
DQ16
DQ17
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5678
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ9
DQ10
DQ11
DQ12
DQ13
VEXT
11
TMS
DNU4
DNU4
QK0
DNU4
DNU4
A1
A4
BA0
BA1
A14
A11
DNU4
DNU4
DNU4
DNU4
DNU4
TDO
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Symbol Description
VDD
Supply voltage
VSS Ground
VDDQ
DQ power supply
VSSQ
DQ Ground
VEXT
Supply voltage
VREF
Reference voltage
VTT Termination voltage
A* Address ‐ A0‐22
BA* Banks ‐ BA0‐2
DQ* I/O
DK* Input data clock(Differential inputs)
QK* Output data clocks(outputs)
CK* Input clocks (CK, CK#)
DM Input data mask
CS#,WE#,REF# Command control pins
ZQ External impedance (25–60Ω)
QVLD
Data valid
DNU,NF Do not use, No function
T* JTAG ‐ TCK,TMS,TDO,TDI
Total
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00E, 06/20/2012
Ball count
16
16
8
12
4
2
4
23
3
18
2
4
2
1
3
1
1
20
4
144
NNoOteTs:ES:
11.) RReesesrevrevde fdorf foutrufreu utuser.e Thuiss em. aTy hopistimonaalyly be
2coo.p Rntenioseencrtaveeldld ty ofob GreN fucDto.unren uescet.e Tdhitso sigGnaNl Dis .internally
c2o)nRneesceterdv aendd fhoasr pfauratusirtiec cuhsaer.acTtehriisstiscisg onf aanl is
ainddterersnsa inllpyuct soignnnael.c Ttheids maanyd ophtaiosnpalalyr baes itic
ccohnanreaccteted rtois GtiNcDs.of an address input signal.
3T. hNios fmunacytioonp. tTihoins saigllnyalb ise inctoenrnnaellcy tceodnnteocted and
h4G3Tha.) NsDiNs po Dmoa nr.aaofysut io utnpisccte ict.oih Tonahanrilas.lc ysTt ibeghenri iacsslto iinscss ini gnoetfnce taaer cnldlai otsloclyk iG cniNnotnpeDnur. etn scaitgelndlay aln. d
hcaosn pnaeracstietidc cahnadrachtaersisptiacsr oafs ai tIi/cO. This may
ocphtaiornaacltlye breis ctoicnsneocftead ctolo GcNkDi.n Npoutet tshiagtn ifa OlD. T is
eTnhaibslemd,a tyheospe tpiionns aarlel yHibghe‐Zc.onnected to
GND.
4) Do not use. This signal is internally
connected and has parasitic
characteristics of a I/O. This may
optionally be connected to GND. Note
that if ODT is enabled, these pins will be
connected to VTT.
3
3Pages IS49NLC96400,IS49NLC18320,IS49NLC36160
2 Electrical Specifications
2.1 Absolute Maximum Ratings
Item
Min
Max
Units
I/O Voltage
0.3
VDDQ + 0.3
V
Voltage on VEXT supply relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
0.3
0.3
0.3
+ 2.8
+ 2.1
+ 2.1
V
V
V
Note: Stress greater than those listed in this table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2.2 DC Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
Max
Units Notes
Supply voltage
Supply voltage
Isolated output buffer supply
Reference voltage
Termination voltage
Input high voltage
Input low voltage
Output high current
VOH = VDDQ/2
VEXT
VDD
VDDQ
VREF
VTT
VIH
VIL
IOH
2.38
1.7
1.4
0.49 x VDDQ
0.95 x VREF
VREF + 0.1
VSSQ 0.3
(VDDQ/2)/
(1.15 x RQ/5)
2.63
1.9
VDD
0.51 x VDDQ
1.05 x VREF
VDDQ + 0.3
VREF 0.1
(VDDQ/2)/
(0.85 x RQ/5)
V
V 2
V 2,3
V 4,5,6
V 7,8
V 2
V 2
A 9, 10, 11
Output low current
VOL = VDDQ/2
IOL
(VDDQ/2)/
(1.15 x RQ/5)
(VDDQ/2)/
(0.85 x RQ/5)
A 9, 10, 11
Clock input leakage current
0V ≤ VIN ≤ VDD
ILC
5
5 µA
Input leakage current
0V ≤ VIN ≤ VDD
ILI
5
5 µA
Output leakage current
0V ≤ VIN ≤ VDDQ
ILO
5
5 µA
Reference voltage current
IREF 5
5 µA
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH (AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL (AC) ≥ –0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD. Control input signals
may not have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ.
5. Peak‐to‐peak AC noise on VREF must not exceed ±2 percent VREF (DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak‐to‐peak noise (non‐common mode) on VREF
may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±2 percent VDDQ/2 for DC error and an additional ±2 percent VDDQ/2 for AC noise.
This measurement is to be taken at the nearest VREF bypass capacitor.
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On‐die termination may be selected using mode register A9 (for non‐multiplexed address mode) or Ax9 (for multiplexed address mode). A resistance RTT from
each data input signal to the nearest VTT can be enabled. RTT = 125–185Ω at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ /2. IOH flows from the device, IOL flows into the device.
10. If MRS bit A8 or Ax8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
2.3 Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
Address / Control Input capacitance
I/O, Output, Other capacitance (DQ, DM, QK, QVLD)
Clock Input capacitance
JTAG pins
CIN
CIO
CCLK
CJ
Note. These parameters are not 100% tested and capacitance is not tested on ZQ pin.
Test Conditions Min Max Units
VIN=0V
1.5 2.5
pF
VIO=0V
3.5 5.0
pF
VCLK=0V
2.0 3.0
pF
VJ=0V
2.0 5.0
pF
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00E, 06/20/2012
6
6 Page | |||
ページ | 合計 : 30 ページ | ||
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部品番号 | 部品説明 | メーカ |
IS49NLC18320 | Common I/O RLDRAM 2 Memory | Integrated Silicon Solution |
IS49NLC18320A | Common I/O RLDRAM 2 Memory | Integrated Silicon Solution |