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PDF IS49FL004T Data sheet ( Hoja de datos )
| Número de pieza | IS49FL004T | |
| Descripción | 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory | |
| Fabricantes | Integrated Silicon Solution | |
| Logotipo |  |
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IS49FL004T
4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
FEATURES
SEPTEMBER 2013
• Single Power Supply Operation
- Low voltage range: 3.0 V - 3.6 V
• Standard Intel Firmware Hub/LPC Interface
- Read compatible to Intel® 82802 Firmware Hub
devices
- Conforms to Intel LPC Interface Specification
Revision 1.1
• Memory Configuration
- IS49FL004: 512K x 8 (4 Mbit)
• Cost Effective Sector/Block Architecture
- IS49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
• Firmware HUB (FWH)/Low Pin Count (LPC)
Mode
- 33 MHz synchronous operation with PCI bus
- 5-signal communication interface for in-system
read and write operations
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
- Register-based read and write protection for
each block (FWH mode only)
- 4 ID pins for multiple Flash chips selection
(FWH mode only)
- 5 GPI pins for General Purpose Input Register
- TBL# pin for hardware write protection to Boot
Block
- WP# pin for hardware write protection to whole
memory array except Boot Block
• Top Boot Block
- IS49FL004: 64 Kbyte top Boot Block
• Automatic Erase and Program Operation
- Build-in automatic program verification for
extended product endurance
- Typical 25 µs/byte programming time
- Typical 50 ms sector/block/chip erase time
• Two Configurable Interfaces
- In-System hardware interface: Auto detection of
Firmware Hub (FWH) or Low Pin Count (LPC)
memory cycle for in-system read and write
operations
- Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
• Address/Address Multiplexed (A/A Mux)
Mode
- 11-pin multiplexed address and 8-pin data I/O
interface
- Supports fast programming on EPROM
programmers
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
• Lower Power Consumption
- Typical 2 mA active read current
- Typical 7 mA program/erase current
• High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
• Compatible Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
• Hardware Data Protection
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A1
9/19/2013
1
1 page  
BLOCK DIAGRAM
TBL#
WP#
INIT#
FWH[3:0] or
LAD[3:0]
FWH4 or LFRAME#
CLK
GPI[4:0]
A[10:0]
I/O[7:0]
WE#
OE#
R/C#
IC
RST#
FWH/LPC
MODE
INTERFACE
PP MODE
INTERFACE
IS49FL004T
ERASE/PROGRAM
VOLTAGE
GENERATOR
HIGH VOLTAGE
SWITCH
I/O BUFFERS
CONTROL
LOGIC
DATA
LATCH
SENSE
AMP
Y-DECODER
X-DECODER
Y-GATING
MEMORY
ARRAY
DEVICE OPERATION
MODE SELECTION
PRODUCT IDENTIFICATION
The IS49FL004 can operate in two configurable
interfaces: The In-System Hardware interface and Ad-
dress/Address Multiplexed (A/A Mux) interface con-
trolled by IC pin. If the IC pin is set to logic high (VIH),
the devices enter into A/A Mux interface mode. If the IC
pin is set logic low (VIL), the devices will be in in-system
hardware interface mode. During the in-system hard-
ware interface mode, the devices can automatically de-
tect the Firmware Hub (FWH) or Low Pin Count (LPC)
memory cycle sent from host system and response to
the command accordingly. The IC pin must be setup
during power-up or system reset, and stays no change
during device operation.
The product identification mode can be used to read the
Manufacturer ID and the Device ID by a software Prod-
uct ID Entry command in both in-system hardware in-
terface and A/A Mux interface modes. The product
indentification mode is activated by three-bus-cycle com-
mand. Refer to Table 1 for the Manufacturer ID and De-
vice ID of IS49FL00x and Table 14 for the SDP Com-
mand Definition.
In FWH mode, the product identification can also be
read directly at FFBC0000h for Manufacturer ID - “9Dh”
and FFBC0001h for Device ID in the 4 GByte system
memory map.
When working in-system, typically on a PC or Notebook,
the IS49FL004 are connected to the host system
through a 5-pin communication interface operated based
on a 33-MHz synchronous clock. The 5-pin interface is
defined as FWH[3:0] and FWH4 pins under FWH mode
or as LAD[3:0] and LFRAME# pins under LPC mode for
easy understanding as to those existing compatible prod-
ucts. When working off-system, typically on a EPROM
Programmer, the devices are operated through 11-pin
multiplexed address - A[10:0] and 8-pin data I/O - I/O[7:
0] interfaces. The memory addresses of devices are in-
put through two bus cycles as row and column addresses
controlled by a R/C# pin.
Table 1: Product Identification
Description
Manufacturer ID
Device ID
IS49FL004
Address
00000h
00002h
4Mb 00001h
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A1
9/19/2013
Data
9Dh
7Fh
6Eh
5
5 Page 
IS49FL004T
FWH MODE OPERATION (CONTINUED)
FWH BYTE PROGRAM WAVEFORMS
CLK
RST# or INIT#
FWH4
FWH[3:0]
CLK
RST# or INIT#
FWH4
FWH[3:0]
CLK
RST# or INIT#
FWH4
FWH[3:0]
CLK
RST# or INIT#
FWH4
FWH[3:0]
Memory
Write
Cycle
1110b
IDSEL
ID[3:0]
1 Clock 1 Clock
xxxxb
x1xxb
Address
IMSIZE
Data
TAR
RSYNC
TAR
xxxxb 0101b 0101b 0101b 0101b 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
Load "5555h" in 7 Clocks
Host to Device
1 Clock Load "AAh" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Device to Host
2nd Start IDSEL
1110b ID[3:0]
1 Clock 1 Clock
xxxxb
x1xxb
Address
IMSIZE
Data
TAR
RSYNC
TAR
xxxxb 0010b 1010b 1010b 1010b 0000b 0101b 0101b 1111b Tri-State 0000b 1111b Tri-State
Load "2AAAh" in 7 Clocks
Host to Device
1 Clock Load "55h" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Device to Host
3rd Start IDSEL
1110b ID[3:0]
1 Clock 1 Clock
xxxxb
x1xxb
Address
IMSIZE
Data
TAR
RSYNC
TAR
xxxxb 0101b 0101b 0101b 0101b 0000b 0000b 1010b 1111b Tri-State 0000b 1111b Tri-State
Load "5555h" in 7 Clocks
Host to Device
1 Clock Load "A0h" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Device to Host
4th Start IDSEL
1110b ID[3:0]
1 Clock 1 Clock
xxxxb
Address
IMSIZE
Data
TAR
RSYNC
TAR
x1xxb A[19:16] A[15:12] A[11:8] A[7:4] A[3:1] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b 1111b Tri-State
Load Address in 7 Clocks
Host to Device
1 Clock Load Data in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Device to Host
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A1
9/19/2013
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS49FL004T.PDF ] | |
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