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RTL8100CLのメーカーはRealtek Microelectronicsです、この部品の機能は「SINGLE-CHIP FAST ETHERNET CONTROLLER」です。 このページではRTL8100CLの詳細な仕様と技術情報(パラメータ、電気的特性、ピン配置など)を見つけることができます. |
RTL8100CL の電気的特性と機能
| 部品番号 | RTL8100CL |
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| 部品説明 | SINGLE-CHIP FAST ETHERNET CONTROLLER | ||
| メーカ | Realtek Microelectronics | ||
| ロゴ |  |
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このページの下部にプレビューとRTL8100CLダウンロード（pdfファイル）リンクがあります。 Total 30 pages
RTL8100C & RTL8100CL
SINGLE-CHIP FAST ETHERNET CONTROLLER
WITH POWER MANAGEMENT
DATASHEET
Rev. 1.06
05 November 2004
Track ID: JATR-1076-21
1 Page  
RTL8100C & RTL8100CL
Datasheet
Table of Contents
1. GENERAL DESCRIPTION...............................................................................................................1
2. FEATURES..........................................................................................................................................2
3. BLOCK DIAGRAM............................................................................................................................3
4. PIN ASSIGNMENTS ..........................................................................................................................4
4.1. RTL8100C (QFP) & RTL8100CL (LQFP).....................................................................................4
5. PIN DESCRIPTION............................................................................................................................5
5.1. POWER MANAGEMENT/ISOLATION INTERFACE ................................................................................5
5.2. PCI INTERFACE ................................................................................................................................6
5.3. EPROM/EEPROM INTERFACE/AUX .............................................................................................8
5.4. POWER PINS .....................................................................................................................................8
5.5. LED INTERFACE...............................................................................................................................8
5.6. ATTACHMENT UNIT INTERFACE .......................................................................................................9
5.7. TEST AND OTHER PINS .....................................................................................................................9
5.8. REGISTER DESCRIPTIONS................................................................................................................10
5.9. RECEIVE STATUS REGISTER IN RX PACKET HEADER.....................................................................12
5.10. TRANSMIT STATUS REGISTER (TSD0-3)(OFFSET 0010H-001FH, R/W) ........................................13
5.11. ERSR: EARLY RX STATUS REGISTER (OFFSET 0036H, R) ............................................................14
5.12. COMMAND REGISTER (OFFSET 0037H, R/W) .................................................................................15
5.13. INTERRUPT MASK REGISTER (OFFSET 003CH-003DH, R/W).........................................................15
5.14. INTERRUPT STATUS REGISTER (OFFSET 003EH-003FH, R/W) .......................................................16
5.15. TRANSMIT CONFIGURATION REGISTER (OFFSET 0040H-0043H, R/W)...........................................17
5.16. RECEIVE CONFIGURATION REGISTER (OFFSET 0044H-0047H, R/W).............................................19
5.17. 9346CR: 93C46 COMMAND REGISTER (OFFSET 0050H, R/W) .....................................................22
5.18. CONFIG 0: CONFIGURATION REGISTER 0 (OFFSET 0051H, R/W)................................................23
5.19. CONFIG 1: CONFIGURATION REGISTER 1 (OFFSET 0052H, R/W)................................................23
5.20. MEDIA STATUS REGISTER (OFFSET 0058H, R/W) ..........................................................................24
5.21. CONFIG 3: CONFIGURATION REGISTER3 (OFFSET 0059H, R/W).................................................25
5.22. CONFIG 4: CONFIGURATION REGISTER4 (OFFSET 005AH, R/W)................................................27
5.23. MULTIPLE INTERRUPT SELECT REGISTER (OFFSET 005CH-005DH, R/W).....................................28
Single-Chip Fast Ethernet Controller
iii
Track ID: JATR-1076-21 Rev. 1.06
3Pages 
RTL8100C & RTL8100CL
Datasheet
List of Tables
Table 1. Power Management/Isolation Interface .........................................................................................5
Table 2. PCI Interface ..................................................................................................................................6
Table 3. EPROM/EEPROM Interface/AUX ...............................................................................................8
Table 4. Power Pins .....................................................................................................................................8
Table 5. LED Interface ................................................................................................................................8
Table 6. Attachment Unit Interface..............................................................................................................9
Table 7. Test and Other Pins ........................................................................................................................9
Table 8. Register Descriptions...................................................................................................................10
Table 9. Receive Status Register in RX Packet Header.............................................................................12
Table 10. Transmit Status Register ..............................................................................................................13
Table 11. ERSR: Early RX Status Register .................................................................................................14
Table 12. Command Register.......................................................................................................................15
Table 13. Interrupt Mask Register ...............................................................................................................15
Table 14. Interrupt Status Register ..............................................................................................................16
Table 15. Transmit Configuration Register .................................................................................................17
Table 16. Receive Configuration Register...................................................................................................19
Table 17. 9346CR: 93C46 Command Register ...........................................................................................22
Table 18. CONFIG 0: Configuration Register 0..........................................................................................23
Table 19. CONFIG 1: Configuration Register 1..........................................................................................23
Table 20. Media Status Register ..................................................................................................................24
Table 21. CONFIG 3: Configuration Register3...........................................................................................25
Table 22. CONFIG 4: Configuration Register4...........................................................................................27
Table 23. Multiple Interrupt Select Register ...............................................................................................28
Table 24. PCI Revision ID...........................................................................................................................28
Table 25. Transmit Status of All Descriptors (TSAD) Register ..................................................................28
Table 26. Basic Mode Control Register.......................................................................................................29
Table 27. Basic Mode Status Register .........................................................................................................29
Table 28. Auto-Negotiation Advertisement Register...................................................................................30
Table 29. Auto-Negotiation Link Partner Ability Register..........................................................................31
Table 30. Auto-Negotiation Expansion Register .........................................................................................32
Table 31. Disconnect Counter......................................................................................................................32
Table 32. False Carrier Sense Counter ........................................................................................................32
Table 33. NWay Test Register......................................................................................................................33
Single-Chip Fast Ethernet Controller ii Track ID: JATR-1076-21 Rev. 1.06
6 Page | |||
| ページ | 合計 : 30 ページ | ||
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PDF ダウンロード | [ RTL8100CL datasheet.PDF ] | |
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RTL8100CL データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 また、RTL8100CLのさまざまなアプリケーション回路とユースケースを使用して独自の設計に統合する方法を理解するのに役立ちます。 |
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| 部品番号 | 部品説明 | メーカ |
| RTL8100C | SINGLE-CHIP FAST ETHERNET CONTROLLER | Realtek Microelectronics |
| RTL8100CL | SINGLE-CHIP FAST ETHERNET CONTROLLER | Realtek Microelectronics |