|
|
PDF IS65WV1288DALL Data sheet ( Hoja de datos )
| Número de pieza | IS65WV1288DALL | |
| Descripción | ULTRA LOW POWER CMOS STATIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS65WV1288DALL (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
128K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
OCTOBER 2009
FEATURES
• High-speed access time: 35ns, 45ns, 55ns
• CMOS low power operation:
12 mW (typical) operating
4 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply:
1.65V--2.2V Vdd (62WV1288DALL)
2.3V--3.6V Vdd (62WV1288DBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and automotive temperature support
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS62/65WV1288DALL and IS62/65WV1288DBLL
are high-speed, 1M bit static RAMs organized as
128K words by 8 bits. It is fabricated using ISSI's high-
performance CMOS technology.This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is low
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65WV1288DALL and IS62/65WV1288DBLL are
packaged in the JEDEC standard 32-pin TSOP (TYPEI),
sTSOP (TYPEI), SOP, and 36-pin mini BGA.
A0-A16
VDD
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
CS2
CS1
OE
WE
CONTROL
CIRCUIT
128K x 8
MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/09
1
1 page  
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol Parameter
Test Conditions
Min.
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –1 mA
2.4
Vol
Output LOW Voltage
Vdd = Min., Iol = 2.1 mA
—
Vih
Input HIGH Voltage
2
Vil
Input LOW Voltage(1)
–0.3
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
–1
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.3V-3.6V
Symbol Parameter
Test Conditions
Min.
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –1.0 mA
1.8
Vol
Output LOW Voltage
Vdd = Min., Iol = 2.1 mA
—
Vih
Input HIGH Voltage
2.0
Vil
Input LOW Voltage(1)
–0.3
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
–1
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol Parameter
Test Conditions
Vdd
Min.
Voh
Output HIGH Voltage
Ioh = -0.1 mA
1.65-2.2V
1.4
Vol
Output LOW Voltage
Iol = 0.1 mA
1.65-2.2V
—
Vih
Input HIGH Voltage
1.65-2.2V
1.4
Vil(1)
Input LOW Voltage
1.65-2.2V
–0.2
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
–1
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
—
0.2
Vdd + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/09
5
5 Page 
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CS1 ≥ Vdd – 0.2V
Com.
Ind.
Auto.
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note: 1. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
Min. typ.(1) Max. Unit
1.2 3.6 V
— 0.5 2 µA
4
18
0 — ns
trc — ns
DATA RETENTION WAVEFORM (CS1 Controlled)
tSDR
Data Retention Mode
VDD
tRDR
VDR
CS1
GND
CS1 ≥ VDD - 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
VDD
CS2
VDR
GND
Data Retention Mode
tSDR
CS2 ≤ 0.2V
tRDR
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/09
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet IS65WV1288DALL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS65WV1288DALL | ULTRA LOW POWER CMOS STATIC RAM | ISSI |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |