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PDF HX8352-C Data sheet ( Hoja de datos )

Número de pieza HX8352-C
Descripción TFT Mobile Single Chip Driver
Fabricantes Himax 
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( DOC No. HX8352-C(T)-DS )
HX8352-C(T)
240RGB x 432 dot, 262K color,
with internal GRAM,
TFT Mobile Single Chip Driver
Temporary version 01 April, 2010

1 page




HX8352-C pdf
HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
April, 2010
Figure 4.1: 8080 System interface protocol, write/read register .................................................... 28
Figure 4.2: 8080 System interface protocol, write/read GRAM...................................................... 28
Figure 4.3: Example of I80 8-bit bus interface ............................................................................... 29
Figure 4.4: Write data for RGB 5-6-5 bits input in I80 8-bit parallel bus interface.......................... 29
Figure 4.5: Write data for RGB 6-6-6 bits input in I80 8-bit parallel bus interface ......................... 30
Figure 4.6: Example of I80 9-bit bus interface ............................................................................... 31
Figure 4.7: Write data for RGB 6-6-6 bits input in I80 9-bit parallel bus interface ......................... 31
Figure 4.8: Example of I80 16-Bit parallel bus interface ................................................................ 32
Figure 4.9: Write data for RGB 5-6-5 bits input in I80 16-bit parallel bus interface ....................... 33
Figure 4.10: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (DFM=0) ...... 34
Figure 4.11: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=07h) . 35
Figure 4.12: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=04h) . 36
Figure 4.13: Example of I80 18-Bit parallel bus interface .............................................................. 37
Figure 4.14: Write data for RGB 6-6-6 bits input in I80 18-bit parallel bus interface ..................... 38
Figure 4.15: Index register read/write timing in 3-wire serial bus system interface ....................... 42
Figure 4.16: Data write timing in 3-wire serial bus system interface.............................................. 43
Figure 4.17: Index register write timing in 4-wire serial bus system interface ............................... 44
Figure 4.18: Data write timing in 4-wire serial bus system interface.............................................. 44
Figure 4.19: PCLK cycle................................................................................................................. 45
Figure 4.20: General Timing Diagram............................................................................................ 46
Figure 4.21: DPI timing diagram .................................................................................................... 46
Figure 4.22: 16 bit data bus color order on DPI interface .............................................................. 47
Figure 4.23: 18 bit data bus color order on DPI interface .............................................................. 48
Figure 5.1: MCU to Memory write / read direction ......................................................................... 52
Figure 5.2: MY, MX, MV setting ..................................................................................................... 52
Figure 5.3: Address direction settings............................................................................................ 53
Figure 5.4: 240RGB x 432 resolution............................................................................................. 54
Figure 5.5: Vertical scrolling ........................................................................................................... 56
Figure 5.6: Memory map of vertical scrolling 1 .............................................................................. 56
Figure 5.7: Memory map of vertical scrolling 2 .............................................................................. 57
Figure 5.8: Vertical scroll example 1 .............................................................................................. 58
Figure 5.9: Vertical scroll example 2 .............................................................................................. 58
Figure 5.10: Tearing Effect Output signal mode 1 ......................................................................... 59
Figure 5.11: TE Delay Output......................................................................................................... 59
Figure 5.12: Tearing Effect Output signal mode 2 ......................................................................... 60
Figure 5.13: TE Output for TELINE setting .................................................................................... 60
Figure 5.14: Tearing Effect Output signal ...................................................................................... 60
Figure 5.15: Tearing Effect Line Timing ......................................................................................... 61
Figure 5.16: Rise and Fall times of TE signal ................................................................................ 61
Figure 5.17: Tearing Effect - Example 1-1 ..................................................................................... 62
Figure 5.18: Tearing Effect - Example 1-2 ..................................................................................... 62
Figure 5.19: Tearing Effect - Example 2-1 ..................................................................................... 63
Figure 5.20: Tearing Effect - Example 2-2 ..................................................................................... 63
Figure 5.21: OSC aritecture ........................................................................................................... 64
Figure 5.22: Source channels of different inversion mode............................................................. 65
Figure 5.23: Scan direction of Gate Driver..................................................................................... 66
Figure 5.24: LCD power generation scheme ................................................................................. 67
Figure 5.25: Block diagram of HX8352-C power circuit with internal charge pump....................... 68
Figure 5.26: Gamma adjustments different of source driver with digital gamma correction .......... 70
Figure 5.27: Grayscale Control ...................................................................................................... 71
Figure 5.28: Structure of Grayscale Voltage Generator................................................................. 72
Figure 5.29: Gamma Resister Steam and Reference Voltage....................................................... 73
Figure 5.30: Relationship between source output and Vcom ........................................................ 81
Figure 5.31: Relationship between data and output level, REV =0, normal white......................... 81
Himax Confidential Temporary Version
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
- P.5-
April, 2010

5 Page





HX8352-C arduino
HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
2. Features
DATA SHEET Temporary V01
2.1 Display
Single chip solution for a 240 x 432 type TFT LCD display
Resolution: 240RGB x 432
Display color modes
262K colours (18-bit 6(R):6(G):6(B))
65K colours (16-bit 5(R):6(G):5(B))
8 colors (Idle mode on): 8 colors (3-bit binary mode)
2.2 Display module
Support 720 source channel outputs
Supports 1-line / n-line/ frame inversion
On module VCOM control (VCOMH= 3.0V to (DDVDH-0.5)V; VCOML=(VCL+0.5)V to 0V)
Charge bump circuit for source, glass gate level shifter
DDVDH= 4.5V to 6.0V
Source output voltage level: VREG1= 4.0V to 5.5V
Positive gate driver output voltage level: VGH= 10V to 18V
Negative gate driver output voltage level: VGL= -5V to -12.5V
Frame memory area 240 (H) x 432 (V) x 18-bit
Himax Confidential Temporary Version
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.11-
April, 2010

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