HX8352-C01 Datasheet PDF - Himax
| Part Number | HX8352-C01 | |
| Description | TFT Mobile Single Chip Driver | |
| Manufacturers | Himax | |
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There is a preview and HX8352-C01 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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( DOC No. HX8352-C01(T)-DS )
HX8352-C01(T)
240RGB x 432 dot, 262K color,
with internal GRAM,
TFT Mobile Single Chip Driver
Version 01 May, 2011
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HX8352-C01(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
May, 2011
Figure 4.1: 8080 System interface protocol, write/read register .................................................... 28
Figure 4.2: 8080 System interface protocol, write/read GRAM...................................................... 28
Figure 4.3: Example of I80 8-bit bus interface ............................................................................... 29
Figure 4.4: Write data for RGB 5-6-5 bits input in I80 8-bit parallel bus interface.......................... 29
Figure 4.5: Write data for RGB 6-6-6 bits input in I80 8-bit parallel bus interface ......................... 30
Figure 4.6: Example of I80 9-bit bus interface ............................................................................... 31
Figure 4.7: Write data for RGB 6-6-6 bits input in I80 9-bit parallel bus interface ......................... 31
Figure 4.8: Example of I80 16-Bit parallel bus interface ................................................................ 32
Figure 4.9: Write data for RGB 5-6-5 bits input in I80 16-bit parallel bus interface ....................... 33
Figure 4.10: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (DFM=0) ...... 34
Figure 4.11: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=07h) . 35
Figure 4.12: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=04h) . 36
Figure 4.13: Example of I80 18-Bit parallel bus interface .............................................................. 37
Figure 4.14: Write data for RGB 6-6-6 bits input in I80 18-bit parallel bus interface ..................... 38
Figure 4.15: Index register read/write timing in 3-wire serial bus system interface ....................... 42
Figure 4.16: Data write timing in 3-wire serial bus system interface.............................................. 43
Figure 4.17: Index register write timing in 4-wire serial bus system interface ............................... 44
Figure 4.18: Data write timing in 4-wire serial bus system interface.............................................. 44
Figure 4.19: PCLK cycle................................................................................................................. 45
Figure 4.20: General Timing Diagram............................................................................................ 46
Figure 4.21: DPI timing diagram .................................................................................................... 46
Figure 4.22: 16 bit data bus color order on DPI interface .............................................................. 47
Figure 4.23: 18 bit data bus color order on DPI interface .............................................................. 48
Figure 5.1: MCU to Memory write / read direction ......................................................................... 52
Figure 5.2: MY, MX, MV setting ..................................................................................................... 52
Figure 5.3: Address direction settings............................................................................................ 53
Figure 5.4: 240RGB x 432 resolution............................................................................................. 54
Figure 5.5: Vertical scrolling ........................................................................................................... 56
Figure 5.6: Memory map of vertical scrolling 1 .............................................................................. 56
Figure 5.7: Memory map of vertical scrolling 2 .............................................................................. 57
Figure 5.8: Vertical scroll example 1 .............................................................................................. 58
Figure 5.9: Vertical scroll example 2 .............................................................................................. 58
Figure 5.10: Tearing Effect Output signal mode 1 ......................................................................... 59
Figure 5.11: TE Delay Output......................................................................................................... 59
Figure 5.12: Tearing Effect Output signal mode 2 ......................................................................... 60
Figure 5.13: TE Output for TELINE setting .................................................................................... 60
Figure 5.14: Tearing Effect Output signal ...................................................................................... 60
Figure 5.15: Tearing Effect Line Timing ......................................................................................... 61
Figure 5.16: Rise and Fall times of TE signal ................................................................................ 61
Figure 5.17: Tearing Effect - Example 1-1 ..................................................................................... 62
Figure 5.18: Tearing Effect - Example 1-2 ..................................................................................... 62
Figure 5.19: Tearing Effect - Example 2-1 ..................................................................................... 63
Figure 5.20: Tearing Effect - Example 2-2 ..................................................................................... 63
Figure 5.21: OSC aritecture ........................................................................................................... 64
Figure 5.22: Source channels of different inversion mode............................................................. 65
Figure 5.23: Scan direction of Gate Driver..................................................................................... 66
Figure 5.24: LCD power generation scheme ................................................................................. 67
Figure 5.25: Block diagram of HX8352-C01 power circuit with internal charge pump................... 68
Figure 5.26: Gamma adjustments different of source driver with digital gamma correction .......... 70
Figure 5.27: Grayscale Control ...................................................................................................... 71
Figure 5.28: Structure of Grayscale Voltage Generator................................................................. 72
Figure 5.29: Gamma Resister Steam and Reference Voltage....................................................... 73
Figure 5.30: Relationship between source output and Vcom ........................................................ 81
Figure 5.31: Relationship between data and output level, REV =0, normal white......................... 81
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
- P.5-
May, 2011
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