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HX8352-B01 の電気的特性と機能

HX8352-B01のメーカーはHimaxです、この部品の機能は「TFT Mobile Single Chip Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 HX8352-B01
部品説明 TFT Mobile Single Chip Driver
メーカ Himax
ロゴ Himax ロゴ 




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HX8352-B01 Datasheet, HX8352-B01 PDF,ピン配置, 機能
DATA SHEET
( DOC No. HX8352-B01-DS )
HX8352-B01(T)
240RGB x 432 dot, 262K color,
with internal GRAM,
TFT Mobile Single Chip Driver
Preliminary version 01 November, 2009

1 Page





HX8352-B01 pdf, ピン配列
HX8352-B01(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
November, 2008
7.10 Input / output pin state ................................................................................................................. 162
7.10.1 Output pins ......................................................................................................................... 162
7.10.2 Input pins ............................................................................................................................ 162
8. Command .............................................................................................................................................. 163
8.1 Command set .............................................................................................................................. 163
8.2 Index register ............................................................................................................................... 170
8.3 Display mode control register (PAGE0 - R00h) ........................................................................... 170
8.4 Display mode control register (PAGE0 - R01h) ........................................................................... 170
8.5 Column address start register (PAGE0 - R02~03h) .................................................................... 172
8.6 Column address end register (PAGE0 - R04~05h) ..................................................................... 173
8.7 Row address start register (PAGE0 - R06~07h) ......................................................................... 173
8.8 Row address end register (PAGE0 - R08~09h) .......................................................................... 173
8.9 Partial area start row register (PAGE0 - R0A~0Bh) .................................................................... 174
8.10 Partial area end row register (PAGE0 - R0C~0Dh) ..................................................................... 175
8.11 Vertical scroll top fixed area register (PAGE0 - R0E~0Fh).......................................................... 176
8.12 Vertical scroll height area register (PAGE0 - R10~11h) .............................................................. 176
8.13 Vertical scroll button fixed area register (PAGE0 - R12~13h) ..................................................... 176
8.14 Vertical scroll start address register (PAGE0 - R14~15h) ........................................................... 178
8.15 Memory access control register (PAGE0 - R16h) ....................................................................... 179
8.16 COLMOD control register (PAGE0 - R17h) ................................................................................. 180
8.17 OSC control register (PAGE0 - R18h & R19h) ............................................................................ 181
8.18 Power control 1 register (PAGE0 - R1Ah) ................................................................................... 182
8.19 Power control 2 register (PAGE0 - R1Bh) ................................................................................... 183
8.20 Power control 3 register (PAGE0 - R1Ch) ................................................................................... 184
8.21 Power control 4 register (PAGE0 - R1Dh) ................................................................................... 184
8.22 Power control 5 register (PAGE0 - R1Eh) ................................................................................... 185
8.23 Power control 6 register (PAGE0 - R1Fh) ................................................................................... 185
8.24 Read data register (PAGE0 - R22h) ............................................................................................ 187
8.25 VCOM control 1~3 register (PAGE0 - R23~25h)......................................................................... 187
8.26 Display control 1~3 register (PAGE0 - R26h~R28h) ................................................................... 190
8.27 Frame control 1~4 register (PAGE0 - R29h~R2Ch).................................................................... 193
8.28 Cycle control 1~2 register (PAGE0 - R2Dh~R2Eh)..................................................................... 195
8.29 Display inversion register (PAGE0 - R2Fh) ................................................................................. 196
8.30 RGB interface control 1~4 register (PAGE0 - R31h~R34h) ........................................................ 196
8.31 OTP contril 1~4 register (PAGE0 - R38h ~ R3Bh) ...................................................................... 198
8.32 CABC control 1~4 register (PAGE0 - R3Ch~3Fh)....................................................................... 199
8.33 Gamma control 1~35 register (PAGE0 - R40h~5Dh) .................................................................. 201
8.34 TE mode control (PAGE0 - R60h) ............................................................................................... 206
8.35 ID1~4 register (PAGE0 - R61h~64h)........................................................................................... 207
8.36 MDDI control 4~5 register (PAGE0 - R68h~R69h)...................................................................... 208
8.37 GPIO control 1~5 register (PAGE0 - R6Bh~R6Fh) ..................................................................... 208
8.38 SUB_PANEL control 1~4 register (PAGE0 - R70h~R73h) .......................................................... 210
8.39 Column address counter 2~1 register (PAGE0 - R80h~R81h) ....................................................211
8.40 Row address counter 2~1 register (PAGE0 - R82h~R83h)......................................................... 212
8.41 Set TE output delay line resgiter2~1 (R84~R85h) ...................................................................... 213
8.42 OTP Control 5~6 (R87h).............................................................................................................. 214
8.43 Command page select register (RFFh) ....................................................................................... 214
8.44 DGC control register (PAGE1 – R00h) ........................................................................................ 214
8.45 DGC LUT1~192 register (PAGE1 – R01h~C0h) ......................................................................... 215
8.46 CABC control 5~7 register (PAGE1 – RC3h, RC5h, RC7h)........................................................ 215
8.47 Gain select register 0~8 (PAGE1 – RCBh~D3h)......................................................................... 216
8.48 Power saving counter 1~4 (PAGE0 – RE4h~E7h) ...................................................................... 218
9. Layout Recommendation .................................................................................................................... 220
9.1 Maximum layout resistance ......................................................................................................... 221
9.2 External components connection ................................................................................................ 222
Himax Confidential
-P.2-
This information contained herein is the exclusive
in whole or in part without prior written permission
property of
of Himax.
Himax
and
shall
not
be
distributed,
reproduced,
or
disclosed
November,
2008


3Pages


HX8352-B01 電子部品, 半導体
HX8352-B01(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
November, 2008
Figure 5.37 RGB 16-bit/pixel on 16-bit data width ............................................................................ 58
Figure 5.38 RGB 18-bit/pixel on 18-bit data width ............................................................................ 59
Figure 5.39 Physical connection of MDDI host and client ................................................................ 60
Figure 5.40 MDDI terminology .......................................................................................................... 61
Figure 5.41 Example of bi-directional MDDI communication ............................................................ 61
Figure 5.42 Data-STB encoding........................................................................................................ 62
Figure 5.43 Data / STB generation & recovery circuit....................................................................... 62
Figure 5.44 Differential connection between host and client ............................................................ 63
Figure 5.45 MDDI packet structure ................................................................................................... 64
Figure 5.46 Panel read is faster than MPU write .............................................................................. 67
Figure 5.47 Panel read is slower than MPU write............................................................................. 68
Figure 5.48 MDDI transceiver / receiver state in hibernation............................................................ 69
Figure 5.49 Host-initiated link wakeup sequence ............................................................................. 70
Figure 5.50 Client-initiated link wake-up sequence .......................................................................... 71
Figure 5.51 MDDI operation mode.................................................................................................... 78
Figure 5.52 Sub panel interface ........................................................................................................ 80
Figure 5.53 Main/sub panel selection procedure .............................................................................. 81
Figure 5.54 18-/16-bit sub panel interface register access data timing for I80 series TFT sub panel
................................................................................................................................................... 82
Figure 5.55 9-/8-bit sub panel interface register access data timing for I80 series TFT sub panel .. 82
Figure 5.56 18-/16-bit sub panel interface register access data timing for I80 series TFT sub panel
................................................................................................................................................... 83
Figure 5.57 9-/8-bit sub panel interface register access data timing for M68 series TFT sub panel 83
Figure 5.58 18-bit sub panel interface video data timing for I80 series TFT sub panel .................... 84
Figure 5.59 18-bit sub panel interface video data timing for M68 series TFT sub panel .................. 84
Figure 5.60 16-bit sub panel interface video data timing for I80 series TFT sub panel .................... 85
Figure 5.61 16-bit sub panel interface video data timing for M68 series TFT sub panel .................. 85
Figure 5.62 9-bit sub panel interface video data timing for I80 series TFT sub panel ...................... 86
Figure 5.63 9-bit sub panel interface video data timing for M68 series TFT sub panel .................... 86
Figure 5.64 8-bit sub panel interface video data timing for I80 series TFT sub panel ...................... 87
Figure 5.65 8-bit sub panel interface video data timing for M68 series TFT sub panel .................... 87
Figure 5.66 18-/16-bit sub panel interface register access data timing for I80 series STN sub panel
................................................................................................................................................... 88
Figure 5.67 9-/8-bit sub panel interface register access data timing for I80 series STN sub panel . 88
Figure 5.68 18-/16-bit sub panel interface register access data timing for M68 series STN sub panel
................................................................................................................................................... 89
Figure 5.69 9-/8-bit sub panel interface register access data timing for M68 series STN sub panel 89
Figure 5.70 18-bit sub panel interface video data timing for I80 series STN sub panel ................... 90
Figure 5.71 18-bit sub panel interface video data timing for M68 series STN sub panel ................. 90
Figure 5.72 16-bit sub panel interface video data timing for I80 series STN sub panel ................... 91
Figure 5.73 16-bit sub panel interface video data timing for M68 series STN sub panel ................. 91
Figure 5.74 9-bit sub panel interface video data timing for I80 series STN sub panel ..................... 92
Figure 5.75 9-bit sub panel interface video data timing for M68 series STN sub panel ................... 92
Figure 5.76 8-bit sub panel interface video data timing for I80 series STN sub panel ..................... 93
Figure 5.77 8-bit sub panel interface video data timing for M68 series STN sub panel ................... 93
Figure 6.1 Image data sending order from host................................................................................ 96
Figure 6.2 MY, MX, MV setting of 240RGB x 432 dot ...................................................................... 96
Figure 6.3 Example for rotation with MY, MX and MV – 1 ................................................................ 99
Figure 6.4 Example for rotation with MY, MX and MV - 2............................................................... 100
Figure 6.5 Partial display area setting (240x432 panel).................................................................. 104
Figure 6.6 Vertical scrolling ............................................................................................................. 105
Figure 6.7 Memory map of vertical scrolling 1 ................................................................................ 105
Figure 6.8 Memory map of vertical scrolling 2 ................................................................................ 106
Figure 6.9 Memory map of vertical scrolling 3 ................................................................................ 106
Figure 6.10 Vertical scrolling example ............................................................................................ 107
Himax Confidential
-P.5-
This information contained herein is the exclusive
in whole or in part without prior written permission
property of
of Himax.
Himax
and
shall
not
be
distributed,
reproduced,
or
disclosed
November,
2008

6 Page



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部品番号部品説明メーカ
HX8352-B00

TFT Mobile Single Chip Driver

Himax
Himax
HX8352-B01

TFT Mobile Single Chip Driver

Himax
Himax


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