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IS45S32200E の電気的特性と機能
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IS45S32200EのメーカーはISSIです、この部品の機能は「SYNCHRONOUS DYNAMIC RAM」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 IS45S32200E |
| 部品説明 SYNCHRONOUS DYNAMIC RAM |
| メーカ ISSI |
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IS42S32200E
IS45S32200E
512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
AUGUST 2009
FEATURES
• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length:
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 16ms (A2 grade) or
64ms (Commercia, Industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42/45S32200E is
organized as 524,288 bits x 32-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All inputs
and outputs signals refer to the rising edge of the clock
input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-5 -6
5 6
10 10
200 166
100 100
5 5.5
8 8
-7 -75E Unit
7 –
10 7.5
ns
ns
143 – Mhz
100 133 Mhz
5.5 –
8 5.5
ns
ns
OPTIONS
• Packages:
86-pin TSOP-II
90-ball TF-BGA
• Operating temperature range:
Commercial (0oC to + 70oC)
Industrial (-40oC to + 85oC)
Automotive Grade, A1 (-40oC to + 85oC)
Automotive Grade, A2: (-40oC to +105oC)
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
07/23/09
1
1 Page
IS42S32200E, IS45S32200E
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PIN DESCRIPTIONS
A0-A10
Row Address Input
A0-A7
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ31 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
86 VSS
85 DQ15
84 VSSQ
83 DQ14
82 DQ13
81 VDDQ
80 DQ12
79 DQ11
78 VSSQ
77 DQ10
76 DQ9
75 VDDQ
74 DQ8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 NC
56 DQ31
55 VDDQ
54 DQ30
53 DQ29
52 VSSQ
51 DQ28
50 DQ27
49 VDDQ
48 DQ26
47 DQ25
46 VSSQ
45 DQ24
44 VSS
WE
DQM0-DQM3
Vdd
Vss
Vddq
Vssq
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
07/23/09
3
3Pages
IS42S32200E, IS45S32200E
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A7 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A7. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
banks(s) is executed after passage of the period tRP, which
is the period required for bank precharging. Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the pre-
charge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without
requiring an explicit command. A10 to enables the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
6
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation. Thestipulatedperiod(trc) is
required for a single refresh operation, and no other com-
mands can be executed during this period. This command
is executed at least 4096 times every tref. During an AUTO
REFRESH command, address bits are “Don’t Care”. This
command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are gen-
erated automatically internally. SELF REFRESH can be
used to retain data in the SDRAM without external clocking,
even if the rest of the system is powered down. The SELF
REFRESH operation is started by dropping the CKE pin
from HIGH to LOW. During the SELF REFRESH operation
all other inputs to the SDRAM become “Don’t Care”.The
device must remain in self refresh mode for a minimum
period equal to tras or may remain in self refresh mode
for an indefinite period beyond that.The SELF-REFRESH
operation continues as long as the CKE pin remains LOW
and there is no need for external control of any other pins.
The next command cannot be executed until the device
internal recovery period (trc) has elapsed. Once CKE
goes HIGH, the NOP command must be issued (minimum
of two clocks) to provide time for the completion of any
internal refresh in progress. After the self-refresh, since it
is impossible to determine the address of the last row to
be refreshed, an AUTO-REFRESH should immediately be
performed for all addresses.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
07/23/09
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| IS45S32200C1 | SYNCHRONOUS DYNAMIC RAM | ISSI |
| IS45S32200E | SYNCHRONOUS DYNAMIC RAM | ISSI |