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TDA8037 の電気的特性と機能

TDA8037のメーカーはNXP Semiconductorsです、この部品の機能は「Low power 3V smart card interface」です。


製品の詳細 ( Datasheet PDF )

部品番号
TDA8037
部品説明
Low power 3V smart card interface
メーカ
NXP Semiconductors
ロゴ

NXP Semiconductors ロゴ 




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TDA8037 Datasheet, TDA8037 PDF,ピン配置, 機能
TDA8037
Low power 3V smart card interface
Rev. 1.1 — 17 November 2014
Product data sheet
1. General description
The TDA8037 is the cost efficient successor of the established integrated contact smart
card reader IC TDA8035. It offers a high level of security for the card performing current
limitation, short circuit detection, ESD protection as well as supply supervision. Operating
in 3 V supply domain, the current consumption during the shutdown mode of the contact
reader is very low. It is therefore the ideal component for a power efficient contact reader.
2. Features and benefits
2.1 Protection of the contact smart card
Thermal and short-circuit protection on all card contacts
VCC regulation:
3 V 5 % on 2 220 nF multilayer ceramic capacitors with low ESR
Current spikes of 40 nA up to 20 MHz, with controlled rise and fall times, filtered
overload detection approximately 120 mA
Automatic activation and deactivation sequences initiated by software or by hardware
in the event of a short-circuit, card take-off, overheating, VDDhost, VREG and VDD
dropping
Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)
Supply supervisor for killing spikes during power on and off:
threshold internally fixed
externally by a resistor bridge (with SO28 package only)
2.2 Easy integration into your contact reader
SW compatible to TDA8024, TDA8034 and TDA8035
3 V smart card supply
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)
External clock input up to 20 MHz
Card clock generation up to 20 MHz using pin CLKDIV with synchronous frequency
changes of fCLKIN, fCLKIN/2 (with SO28 package only)
Non-inverted control of pin RST using pin RSTIN
Built-in debouncing on card presence contact
Multiplexed status signal using pin OFFN
Chip Select digital input for parallel operation of several TDA8037 ICs (with SO28
package only)

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TDA8037 pdf, ピン配列
NXP Semiconductors
6. Block diagram
VDDhost
TDA8037
Low power 3V smart card interface
VDD
10 µF
100 nF
VDD
CS
CMDVCCN
CLKDIV
RSTIN
LATCH
I/OUC
AUX1UC
UC
AUX2UC
HOST
INTERFACE
HZ
VDD
PORADJ GND
VDD
TEST
INTERNAL
REGULATOR
reset and
input
supalarm
sense SUPERVISOR
BANDGAP
INTERNAL OSCILLATOR
configurations
bus for smartcard THERMAL PROTECTION
reader interface
interruption
DIGITAL
SEQUENCER
ISO7816
READER
INTERFACE
VCC
RST
2x
220 nF
CLK
AUX1
AUX2
I/O
CARD
CONNECTOR
c5 c1
c6 c2
c7 c3
c8 c4
CLOCK CIRCUITRY
CLKIN
OFFN
HZ
TDA8037
PRESN
Fig 1. Block diagram
aaa-011372
TDA8037
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 17 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 29


3Pages


TDA8037 電子部品, 半導体
NXP Semiconductors
TDA8037
Low power 3V smart card interface
8. Functional description
Remark: The ISO 7816 terminology convention has been adhered to throughout this
document, and it is assumed that the reader is familiar with this convention.
8.1 Power supply
Power supply voltage VDD is from 3 V to 3.6 V.
All interface signals with the system controller are referenced to VDD. All card contacts
remain inactive during powering up or powering down.
Internal regulator VREG is 1.8 V.
After powering the device, OFFN remains low until CMDVCCN is set high and PRESN is
low.
During power off, OFFN falls low when VDD is below the threshold voltage falling.
The frequency of the internal oscillator (fosc(int)) used for the activation sequences is put in
low frequency mode. It is to save power consumption while CMDVCCN is kept at high
level (card not activated).
8.2 Voltage supervisor
VDD
VREG
VDDhost
PORADJ
VDD
REFERENCE
VOLTAGE
Nand
TDA8037
Product data sheet
aaa-011375
Fig 4. Block voltage supervisor
The voltage supervisor is used as a power-on reset, and also as supply drop detection
during a card session. The threshold of the voltage supervisor is set internally in the IC for
VDD and VREG. The threshold can be adjusted externally for VDDhost using the PORADJ
pin. As long as VDD is less than Vth(VDD) + Vhys(VDD), the IC remains inactive whatever the
levels on the command lines are. It lasts during tw after VDD has reached a level higher
than Vth(VDD) + Vhys(VDD).The outputs of the VDD, VREG and VDDhost supervisors, are
combined and sent to a digital controller in order to reset the TDA8037. The defined reset
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 17 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 29

6 Page

合計 : 29 ページ
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