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NT5CB64M16AP の電気的特性と機能
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NT5CB64M16APのメーカーはNanyaです、この部品の機能は「1Gb DDR3 SDRAM A-Die」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 NT5CB64M16AP |
| 部品説明 1Gb DDR3 SDRAM A-Die |
| メーカ Nanya |
ロゴ |
このページの下部にプレビューとNT5CB64M16APダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Feature
1.5V ± 0.075V (JEDEC Standard Power Supply)
8 Internal memory banks (BA0- BA2)
Differential clock input (CK, )
Programmable Latency: 5, 6, 7, 8, 9
Programmable Additive Latency: 0, CL-1, CL-2
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
8 bit prefetch architecture
Output Driver Impedance Control
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
Partial Array Self-Refresh
RoHS Compliance
Packages:
78-Ball BGA for x4 & x8 components
96-Ball BGA for x16 components
Description
The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 1,073,741,824 bits. It is
internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices
achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All
I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.75V power supply and are available in BGA packages.
REV 1.2
01 / 2009
1
1 Page
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Pin Configuration – 78 balls BGA Package (x8)
< TOP View>
See the balls through the package
1
VSS
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
2
VDD
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD
BA0
A3
A5
A7
3
NC
DQ0
DQS
DQ4
BA2
A0
A2
A9
A13
x8
7
A NU/
B DM/TDQS
C DQ1
D VDD
E DQ7
F CK
G
H A10/AP
J NC
K A12/
L A1
M A11
N NC
8
VSS
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VERFCA
BA1
A4
A6
A8
9
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
REV 1.2
01 / 2009
3
3Pages
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Symbol
Type
Function
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3
SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS# and DM/TDQS, NU/TDQS#
ODT
Input
(when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16
configuration ODT is applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU and DML signal.
The ODT pin will be ignored if MR1and MR2 are programmed to disable RTT.
Input
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when
RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail to rail
signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V
NC No Connect: No internal electrical connection is present.
VDDQ
Supply DQ Power Supply: 1.5V ± 0.075V
VDD Supply Power Supply: 1.5V ± 0.075V
VSSQ
Supply DQ Ground
Vss Supply Ground
VREFCA
Supply Reference voltage for CA
VREFDQ
Supply Reference voltage for DQ
ZQ Supply Reference pin for ZQ calibration.
Note: Input only pins (BA0-BA2, A0-A13, , , , , CKE, ODT, and ) do not supply termination.
DDR3 SDRAM Addressing
Configuration
NT5CB256M4AN
NT5CU128M8AN
NT5CB64M16AP
# of Bank
888
Bank Address
BA0 – BA2
BA0 – BA2
BA0 – BA2
Auto precharge
A10 / AP
A10 / AP
A10 / AP
BL switch on the fly
A12 /
A12 /
A12 /
Row Address
A0 – A13
A0 – A13
A0 – A12
Column Address
A0 – A9, A11
A0 – A9
A0 – A9
Page size
1KB 1KB 2KB
Note:
Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command is
registered. Page size is per bank, calculated as follows:
Page size = 2 COLBITS * ORG / 8
COLBITS = the number of column address bits
ORT = the number of I/O (DQ) bits
REV 1.2
01 / 2009
6
6 Page
合計 : 30 ページ |
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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| 部品番号 | 部品説明 | メーカ |
| NT5CB64M16AP | 1Gb DDR3 SDRAM A-Die | Nanya |