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A4952 の電気的特性と機能

A4952のメーカーはAllegroです、この部品の機能は「(A4952 / A4953) Full-Bridge DMOS PWM Motor Drivers」です。


製品の詳細 ( Datasheet PDF )

部品番号
A4952
部品説明
(A4952 / A4953) Full-Bridge DMOS PWM Motor Drivers
メーカ
Allegro
ロゴ

Allegro ロゴ 




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A4952 Datasheet, A4952 PDF,ピン配置, 機能
A4952 and A4953
Full-Bridge DMOS PWM Motor Drivers
Features and Benefits
• Low RDS(on) outputs
• Overcurrent protection (OCP)
Motor short protection
Motor lead short to ground protection
Motor lead short to battery protection
• Low Power Standby mode
• Adjustable PWM current limit
• Synchronous rectification
• Internal undervoltage lockout (UVLO)
• Crossover-current protection
• Fault output (A4952 only)
• Selectable retry (A4952 only)
Packages:
10-pin MSOP
with exposed thermal pad
(LY package)
Description
Designed for pulse width modulated (PWM) control of DC
motors, the A4952 and A4953 are capable of peak output
currents to ±2 A and operating voltages to 40 V.
Input terminals are provided for use in controlling the speed and
direction of a DC motor with externally applied PWM control
signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
Internal circuit protection includes overcurrent protection,
motor lead short to ground or supply, thermal shutdown with
hysteresis, undervoltage monitoring of VBB, and crossover-
current protection.
The A4952 is provided in a low-profile 10-pin MSOP package
(suffix LY) and the A4953 is provided in a low-profile
8-pin SOICN package (suffix LJ). Both packages have an
exposed thermal pad, and are lead (Pb) free, with 100% matte tin
leadframe plating.
8-pin SOICN
with exposed thermal pad
(LJ package)
Not to scale
Functional Block Diagram
A4952 only
RTRY
VINT
IN1
IN2
GND
A4952 only
FLTn
VREF
÷ 10
OSC
Charge
Pump
Control
Logic
Disable
TSD
UVLO
7V
Load Supply
VBB
OUT1
OUT2
LSS
(Optional)
A4952-DS, Rev. 2
Free Datasheet http://www.Datasheet4U.com

1 Page





A4952 pdf, ピン配列
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
ELECTRICAL CHARACTERISTICS Valid at TJ = 25°C, unless otherwise specified
Characteristics
Symbol
Test Conditions
General
Load Supply Voltage Range
RDS(on) Sink + Source Total
Load Supply Current
VBB
RDS(on)
IBB
IOUT = |1.5 A|, TJ = 25°C
IOUT = |1.5 A|, TJ = 125°C
fPWM < 30 kHz
Low Power Standby mode
Body Diode Forward Voltage
Logic I/O Inputs
Vf
Source diode, If = –1.5 A
Sink diode, If = 1.5 A
Logic Input Voltage Range
Logic Input Pull-Down Resistance
Logic Input Current
Input Hysteresis
Logic I/O Inputs (A4952 only)
VIN(1)
VIN(0)
VIN(STANDBY)
RRR LOGIC(PD)
IIN(1)
IIN(0)
VHYS
INx pins
INx pins
INx pins, Low Power Standby mode
VIN = 0 V = IN1 = IN2
INx pins, VIN = 2.0 V
INx pins, VIN = 0.8 V
Retry Input Voltage
Retry Overcurrent Protection Pullup
Voltage
VRTRY RTRY pin = valid
VRTRY(OC) RTRY pin = open
Retry Short Circuit Current
Fault Output Voltage
Fault Output Leakage Current
Timing
IRTRY
VRST
ILK
RTRY pin = GND
FLTn pin, IOUT = 1 mA
FLTn pin, no fault, pull-up to 5 V
Crossover Delay
VREF Input Voltage Range
Current Gain
Blank Time
Constant Off-time
Standby Timer
Power-Up Delay
Protection Circuits
tCOD
VREF
AV
tBLANK
toff
tst
tpu
VREF / ISS , VREF = 5 V
VREF / ISS , VREF = 2.5 V
VREF / ISS , VREF = 1 V
IN1 = IN2 < VIN(STANDBY)
UVLO Enable Threshold
UVLO Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VBBUVLO
VBBUVLOhys
TJTSD
TTSDhys
VBB increasing
Temperature increasing
Recovery = TJTSD – TTSDhys
Min.
8
2.0
50
0
9.5
9.0
8.0
2
16
7
Typ.
0.8
1.3
10
50
40
16
250
3
10
400
3
25
1
7.5
500
160
20
Max.
40
1.0
1.6
10
1.5
1.5
0.8
0.4
100
40
550
200
0.5
1
500
5
10.5
10.0
10.0
4
34
1.5
30
7.95
Unit
V
Ω
Ω
mA
μA
V
V
V
V
V
kΩ
μA
μA
mV
mV
V
μA
V
μA
ns
V
V/V
V/V
V/V
μs
μs
ms
μs
V
mV
°C
°C
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Free
Data


3Pages


A4952 電子部品, 半導体
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Synchronous Rectification
When a PWM off-cycle is triggered by an internal fixed off-time
cycle, load current will recirculate. The A4952/A4953 synchro-
nous rectification feature turns-on the appropriate DMOSFETs
during the current decay, and effectively shorts out the body
diodes with the low RDS(on) driver. This significantly lowers
power dissipation. When a zero current level is detected, syn-
chronous rectification is turned off to prevent reversal of the load
current.
Mixed Decay Operation
The bridges operate in Mixed Decay mode. Referring to the
lower panel of the figure below, as the trip point is reached, the
device goes into fast decay mode for 50% of the fixed off-time
period. After this fast decay portion the device switches to slow
decay mode for the remainder of the off-time. During transitions
from fast decay to slow decay, the drivers are forced off for the
Crossover Delay, tCOD . This feature is added to prevent shoot-
through in the bridge. During this “dead time” portion, synchro-
nous rectification is not active, and the device operates in fast
decay and slow decay only.
Mixed Decay Mode Operation
VPHASE
+
IOUT 0
See Enlargement A
Enlargement A
Fixed Off-Time, toff = 25 μs
0.50 × toff
0.50 × toff
ITrip
IOUT
tCOD
Fast Decay
tCOD
Slow Decay
tCOD
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Free Datasheet http://www.Datasheet4U.com

6 Page

合計 : 11 ページ
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部品番号部品説明メーカ
A4950

Full-Bridge DMOS PWM Motor Driver

Allegro MicroSystems
Allegro MicroSystems
A4952

(A4952 / A4953) Full-Bridge DMOS PWM Motor Drivers

Allegro
Allegro
A4953

(A4952 / A4953) Full-Bridge DMOS PWM Motor Drivers

Allegro
Allegro

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