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AD5696 の電気的特性と機能

AD5696のメーカーはAnalog Devicesです、この部品の機能は「(AD5694 / AD5696) 16-/12-Bit nanoDAC+」です。


製品の詳細 ( Datasheet PDF )

部品番号
AD5696
部品説明
(AD5694 / AD5696) 16-/12-Bit nanoDAC+
メーカ
Analog Devices
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Analog Devices ロゴ 




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AD5696 Datasheet, AD5696 PDF,ピン配置, 機能
Data Sheet
FEATURES
High relative accuracy (INL): ±2 LSB maximum at 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
400 kHz I2C-compatible serial interface
4 I2C addresses available
Low glitch: 0.5 nV-sec
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 1.8 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5696 and AD5694, members of the nanoDAC+™ family,
are low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm ×
3 mm LFCSP package and in a TSSOP package.
The AD5696/AD5694 incorporate a power-on reset circuit and a
RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power
up to zero scale or midscale and remain at that level until a valid
write takes place. The parts contain a per-channel power-down
feature that reduces the current consumption of the device in
power-down mode to 4 µA at 3 V.
The AD5696/AD5694 use a versatile 2-wire serial interface that
operates at clock rates up to 400 kHz and include a VLOGIC pin
intended for 1.8 V/3 V/5 V logic.
Quad, 16-/12-Bit nanoDAC+
with I2C Interface
AD5696/AD5694
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCL
SDA
AD5696/AD5694
INPUT
REGISTER
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
DAC
STRING
REGISTER DAC B
A1
INPUT
DAC
STRING
REGISTER REGISTER DAC C
A0
INPUT
DAC
STRING
REGISTER REGISTER DAC D
POWER-ON
RESET
GAIN =
×1/×2
LDAC RESET
RSTSEL
Figure 1.
GAIN
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
SPI
Internal
AD5686R
External AD5686
I2C
Internal
AD5696R
External AD5696
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5684
AD5694R
AD5694
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5696 (16-bit): ±2 LSB maximum
AD5694 (12-bit): ±1 LSB maximum
2. Excellent DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.Datasheet4U.com

1 Page





AD5696 pdf, ピン配列
Data Sheet
AD5696/AD5694
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE2
AD5696
Resolution
Relative Accuracy
Min
16
Differential Nonlinearity
AD5694
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
12
Offset Error Drift3
Gain Temperature
Coefficient3
DC Power Supply Rejection
Ratio3
DC Crosstalk3
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
Resistive Load4
Load Regulation
0
0
1
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
REFERENCE INPUT
Reference Current
Reference Input Range
Reference Input Impedance
1
1
A Grade
Typ Max
Min
±2 ±8
±2 ±8
±1
16
±0.12
0.4
+0.1
+0.01
±0.02
±0.01
±1
±1
0.15
±2
±3
±2
±2
±1
4
±4
±0.2
±0.2
±0.25
±0.25
12
VREF 0
2 × VREF
0
2
10
1
80
80
40
25
2.5
90
180
VDD
VDD/2
16
32
1
1
B Grade
Typ Max
Unit Test Conditions/Comments1
±1 ±2
±1 ±3
±1
±0.12
0.4
+0.1
+0.01
±0.02
±0.01
±1
±1
0.15
±2
±3
±2
±1
±1
1.5
±1.5
±0.1
±0.1
±0.1
±0.2
VREF
2 × VREF
2
10
80
80
40
25
2.5
90
180
VDD
VDD/2
16
32
Bits
LSB Gain = 2
LSB Gain = 1
LSB Guaranteed monotonic by
design
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
ppm
Guaranteed monotonic by
design
All 0s loaded to DAC register
All 1s loaded to DAC register
Gain = 2
Gain = 1
Of FSR/°C
mV/V
µV
µV/mA
µV
DAC code = midscale; VDD =
5 V ± 10%
Due to single channel, full-
scale output change
Due to load current change
Due to power-down (per
channel)
V
V
nF
nF
kΩ
µV/mA
µV/mA
mA
Ω
µs
Gain = 1
Gain = 2 (see Figure 20)
RL = ∞
RL = 1 kΩ
DAC code = midscale
5 V ± 10%; −30 mA ≤ IOUT
+30 mA
3 V ± 10%; −20 mA ≤ IOUT
+20 mA
See Figure 20
Coming out of power-down
mode; VDD = 5 V
µA VREF = VDD = 5.5 V, gain = 1
µA VREF = VDD = 5.5 V, gain = 2
V Gain = 1
V Gain = 2
kΩ Gain = 2
kΩ Gain = 1
Rev. A | Page 3 of 24
Free Datasheet http://www.Datasheet4U.com


3Pages


AD5696 電子部品, 半導体
AD5696/AD5694
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2 Min
Max Unit Description
t1 2.5
μs SCL cycle time
t2 0.6
μs tHIGH, SCL high time
t3 1.3
μs tLOW, SCL low time
t4 0.6
μs tHD,STA, start/repeated start hold time
t5 100
t63 0
ns
0.9 μs
tSU,DAT, data setup time
tHD,DAT, data hold time
t7 0.6
μs tSU,STA, repeated start setup time
t8 0.6
μs tSU,STO, stop condition setup time
t9 1.3
μs tBUF, bus free time between a stop condition and a start condition
t104 0
300 ns
tR, rise time of SCL and SDA when receiving
t114, 5
20 + 0.1CB
300
ns
tF, fall time of SCL and SDA when transmitting/receiving
t12 20
ns LDAC pulse width
t13 400
ns SCL rising edge to LDAC rising edge
tSP6 0
CB5
50 ns
400 pF
Pulse width of suppressed spike
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL
falling edge.
4 tR and tF are measured from 0.3 × VDD to 0.7 × VDD.
5 CB is the total capacitance of one bus line in pF.
6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
Timing Diagram
START
CONDITION
SDA
t9
SCL
t4
t3
LDAC1
t10
t6
LDAC2
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
REPEATED START
CONDITION
t11 t4
t2
t5
t1
t7
t13
t12
Figure 2. 2-Wire Serial Interface Timing Diagram
STOP
CONDITION
t8 t12
Rev. A | Page 6 of 24
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合計 : 24 ページ
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