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MX25L12845E の電気的特性と機能
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MX25L12845EのメーカーはMacronix Internationalです、この部品の機能は「128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 MX25L12845E |
| 部品説明 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY |
| メーカ Macronix International |
ロゴ |
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MX25L12845E
MX25L12845E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
PRELIMINARY
www.DataSheet4U.com
P/N: PM1428
REV. 0.06, MAR. 05, 2009
1
1 Page
MX25L12845E
(28) Write Protection Selection (WPSEL)................................................................................................................ 31
WPSEL Flow........................................................................................................................................................... 31
(29) Single Block Lock/Unlock Protection (SBLK/SBULK)...................................................................................... 32
Block Lock Flow...................................................................................................................................................... 32
Block Unlock Flow................................................................................................................................................... 33
(30) Read Block Lock Status (RDBLOCK).............................................................................................................. 34
(31) Gang Block Lock/Unlock (GBLK/GBULK)........................................................................................................ 34
(32) Clear SR Fail Flags (CLSR)............................................................................................................................. 35
(33) Enable SO to Output RY/BY# (ESRY)............................................................................................................. 35
(34) Disable SO to Output RY/BY# (DSRY)............................................................................................................ 35
POWER-ON STATE.................................................................................................................................................... 36
ELECTRICAL SPECIFICATIONS.............................................................................................................................. 37
ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 37
Figure 2. Maximum Negative Overshoot Waveform................................................................................................ 37
CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................. 37
Figure 3. Maximum Positive Overshoot Waveform................................................................................................. 37
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL................................................................... 38
Figure 5. OUTPUT LOADING................................................................................................................................ 38
Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ........ 39
Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ..... 40
Timing Analysis......................................................................................................................................................... 42
Figure 6. Serial Input Timing................................................................................................................................... 42
Figure 7. Output Timing........................................................................................................................................... 42
Figure 8. Serial Input Timing for Double Transfer Rate Mode................................................................................. 43
Figure 9. Serial Output Timing for Double Transfer Rate Mode.............................................................................. 43
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...................................................... 44
Figure 11. Write Enable (WREN) Sequence (Command 06).................................................................................. 44
Figure 12. Write Disable (WRDI) Sequence (Command 04)................................................................................... 44
Figure 13. Read Identification (RDID) Sequence (Command 9F)........................................................................... 45
Figure 14. Read Identification (RDID) Sequence (Parallel)..................................................................................... 45
Figure 15. Read Status Register (RDSR) Sequence (Command 05)..................................................................... 46
www.DataSheFeti4gUu.rceom16. Write Status Register (WRSR) Sequence (Command 01).................................................................... 46
Figure 17. Read Data Bytes (READ) Sequence (Command 03)........................................................................... 47
Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B)........................................................ 47
Figure 19. Fast DT Read (FASTDTRD) Sequence (Command 0D)........................................................................ 48
Figure 20. 2 x I/O Read Mode Sequence (Command BB)...................................................................................... 48
Figure 21. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)................................................................ 49
Figure 22. 4 x I/O Read Mode Sequence (Command EB)...................................................................................... 49
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)............................................................... 50
Figure 24. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)................................................. 51
Figure 25. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED).......................... 52
Figure 26. Page Program (PP) Sequence (Command 02)..................................................................................... 53
Figure 27. 4 x I/O Page Program (4PP) Sequence (Command 38)....................................................................... 53
Figure 28. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)........................ 54
Figure 29. Sector Erase (SE) Sequence (Command 20)....................................................................................... 54
Figure 30. Block Erase (BE) Sequence (Command D8)........................................................................................ 54
Figure 31. Chip Erase (CE) Sequence (Command 60 or C7)................................................................................ 55
Figure 32. Deep Power-down (DP) Sequence (Command B9).............................................................................. 55
Figure 33. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)... 55
Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB).................................................... 56
Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)..... 56
Figure 36. READ ARRAY SEQUENCE (Parallel)................................................................................................... 57
Figure 37. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel).................................................................... 58
P/N: PM1428
REV. 0.06, MAR. 05, 2009
3
3Pages
MX25L12845E
• Advanced Security Features
- Flexible block or individual block protect selection
The BP0-BP3 status bits define the size of the area to be software protection against program and erase instruc-
tions
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- Both REMS,REMS2, REMS4 and REMS4D commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Common Flash Interface (CFI)(TBD)
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1/PO7
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode or Parallel Data
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O mode
• NC/SIO3
www.DataShe-eNt4CU.cpoimn or serial data Input/Output for 4 x I/O mode
• PO0~PO6
- For parallel mode data
• PACKAGE
- 16-pin SOP (300mil)
- All Pb-free devices are RoHS Compliant
P/N: PM1428
REV. 0.06, MAR. 05, 2009
6
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| MX25L12845E | 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY | Macronix International |