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QS532805B の電気的特性と機能
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QS532805BのメーカーはIntegrated Device Technologyです、この部品の機能は「GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 QS532805B |
| 部品説明 GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER |
| メーカ Integrated Device Technology |
ロゴ |
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QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
QS532805/A/B
FEATURES:
− JEDEC compatible LVTTL level inputs and outputs
− 10 output, low skew clock signal buffer
− Monitor output
− Clock inputs are 5V tolerant
− Pinout and function compatible with QS5805T
− 25Ω on-chip resistors for low noise
− Input hysteresis for better noise margin
− Guaranteed low skew:
• 0.7ns output skew
• 0.7ns pulse skew
• 1ns part-to-part skew
− Std., A, and B speed grades (B speed in QSOP package only)
− Available in QSOP and SOIC packages
DESCRIPTION
The QS532805 clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of 5 non-inverting outputs. The QS532805 incorporates 25Ω series
termination resistors. This clock buffer product is designed for use in high
performance workstations, embedded and personal computing systems
using 3V to 3.6V supply voltages. Several can be used in parallel or
scattered throughout a system for guaranteed low skew, system-wide clock
distribution networks. The QS532805 can accept 5V input and control
signals.
The QS532805 is characterized for operation at -40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
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OEA
INA
INB
OEB
5
OA5 OA1
MON
5
OB5 OB1
NOTE: QS532805 has a 25Ω series termination resistor on each clock output, including monitor.
INDUSTRIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
JULY 2000
DSC-5785/-
1 Page
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V
Symbol
VIH
VIL
VIC
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Clamp Diode Voltage (3)
Output HIGH Voltage
VOL Output LOW Voltage
IIN
IOZ
IOFF
IODH
IODL
IOS
ROUT
Input Leakage Current
Output Leakage Current
Input Power Off Leakage
Output HIGH Current (2)
Output LOW Current (2)
Short Circuit Current (2,3)
Output Resistance (4)
Test Conditions
Guaranteed Logic HIGH for Inputs
Guaranteed Logic LOW for Inputs
Vcc = Min., IIN = -18mA
Vcc = Min., IOH = -100µA
Vcc = Min., IOH = -8mA
Vcc = Min., IOL = 100µA
Vcc = Min., IOL = 6mA
Vcc = Min., IOL = 8mA
Vcc = Max., VIN = Vcc or GND
Vcc = Max., VOUT = Vcc or GND
Vcc = 0V, VIN = Vcc or GND
Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V
Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V
Vcc = Max., VOUT = GND
Vcc = Min
Min. Typ.(1) Max. Unit
2 — 5.5 V
–0.5 — 0.8 V
— –0.7 –1.2 V
Vcc – 0.2 —
—V
2.4 — — V
— — 0.2 V
— — 0.4 V
— — 0.5 V
— — ±1 µA
— — ±1 µA
— — ±1 µA
–30 –100 –200 mA
30 100 200 mA
– 60 —
— mA
— 28 — Ω
NOTES:
1. Typical values are at VCC = 3.3V, TA = 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
4. Output resistance represents the total output impedence of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
ICC Quiescent Power Supply Current
Test Conditions (1)
VCC = Max., VIN = GND or Vcc
Typ. (3)
0.01
∆ICC Supply Current per Input HIGH
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ICCD Dynamic Power Supply Current per Output (2)
IC Total Power Supply Current Examples (2,4)
VCC = Max., VIN = Vcc – 0.6V, f = 0MHz
VCC = Max., OEA = OEB = GND
Outputs Toggling at 50% duty cycle
VCC = Max.,
OEA = OEB = GND
VIN = GND or Vcc
50% duty cycle, fI = 10MHz VIN = GND or 3V
five outputs toggling
VCC = Max.,
OEA = OEB = GND
VIN = GND or Vcc
50% duty cycle, fI = 2.5MHz VIN = GND or 3V
All outputs toggling
0.1
65
3.3
3.3
1.8
1.8
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. CL = 0pF.
3. Typical values are for reference only. Conditions are VCC = 3.3V, TA = 25°C.
4. IC = ICC + (∆ICC)(DH)(NI) + ICCD (fO)(NO)
where:
DH = Input Duty Cycle
NI = Number of TTL HIGH inputs at DH
fO = Output Frequency
NO = Number of outputs at fO
Max. Unit
100 µA
30 µA
100 µA/MHz
5.2 mA
5.2 mA
2.9 mA
2.9 mA
3
3Pages
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
QS XXXX
Device Type
XX
Package
INDUSTRIALTEMPERATURERANGE
Q Quarter Size Small Outline Pacakge (SO20-8)
SO Small Outline IC (SO20-2)
532805 Guaranteed Low Skew 3.3V CMOS Clock Driver/Buffer
532805A
(532805B) (QSOP package only)
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CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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| 部品番号 | 部品説明 | メーカ |
| QS532805 | GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER | Integrated Device Technology |
| QS532805A | GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER | Integrated Device Technology |
| QS532805B | GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER | Integrated Device Technology |