WV3HG264M72EER-D7 の電気的特性と機能

WV3HG264M72EER-D7のメーカーはWhite Electronic Designsです、この部品の機能は「1GB - 2x64Mx72 DDR2 SDRAM REGISTERED」です。

製品の詳細 ( Datasheet PDF )

部品番号
WV3HG264M72EER-D7

部品説明
1GB - 2x64Mx72 DDR2 SDRAM REGISTERED

メーカ
White Electronic Designs

ロゴ

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WV3HG264M72EER-D7 Datasheet, WV3HG264M72EER-D7 PDF,ピン配置, 機能

White Electronic Designs WV3HG264M72EER-D7

ADVANCED*

1GB – 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM

FEATURES

244-pin, dual in-line memory module (Mini-DIMM)

Fast data transfer rates: PC2-6400*, PCS-5300*,

PC2-4200 and PC2-3200

Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM

components

VCC = VCCQ = 1.8V ±0.1V

VCCSPD = 1.7V to 3.6V

Differential data strobe (DQS, DQS#) option

Four-bit prefetch architecture

Programmable CAS# latency (CL): 3, 4, 5 and 6

On-die termination (ODT)

Serial Presence Detect (SPD) with EEPROM

JEDEC Standard 1.8V I/O (SSTL_18 Compatible)

Gold (Au) edge contacts

Dual Rank

RoHS compliant

Package option

• 244 Pin Mini-DIMM

• PCB – 30.00mm (1.181") TYP

DESCRIPTION

The WV3HG264M72EER is a 2x64Mx72 Double Data

Rate DDR2 SDRAM high density module. This memory

module consists of eighteen 64Mx8 bit with 4 banks DDR2

Synchronous DRAMs in FBGA packages, mounted on a

244-pin DIMM FR4 substrate.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

NOTE: Consult factory for availability of:

• Vendor source control options

• Industrial temperature option

www.DataSheet4U.com

Clock Speed

CL-tRCD-tRP

*Consult factory for availability.

OPERATING FREQUENCIES

PC2-3200

200MHz

3-3-3

PC2-4200

266MHz

4-4-4

PC2-5300*

333MHz

5-5-5

PC2-6400*

400MHz

6-6-6

August 2006

Rev. 3

1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page

White Electronic Designs WV3HG264M72EER-D7

ADVANCED

FUNCTIONAL BLOCK DIAGRAM

RCS1#

RCS0#

DQS0

DQS0#

DM0

DQS1

DQS1#

DM1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS2

DQS2#

DM2

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS3

DQS3#

DM3

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

www.DataSheet4DDQQUSS88.#com

DM8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DQS4#

DM4

CS# DQS DQS#

DQS5

DQS5#

DM5

CS# DQS DQS#

DQS6

DQS6#

DM6

CS# DQS DQS#

DQS7

DQS7#

DM7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

SCL

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DM/

RDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

Serial PD

WP A0 A1 A2

SA0 SA1 SA2

SDA

VCCSPD

VCC/VCCQ

VREF

VSS

Serial PD

DDR2 SDRAMs

CS0#

CS1#

BA0-BA1

A0-A13

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#**

CK#**

CK**

1:2

RST#

RCS0# -> CS# : DDR2 SDRAMs

RCS1 -> CS# : DDR2 SDRAMs

RBA0 - RBA1 -> BA0-BA1 : DDR2 SDRAMs

RA0-RA13 -> A0-A13 : DDR2 SDRAMs

RRAS# -> RAS# DDR2 SDRAMs

RCAS# -> CAS# DDR2 SDRAMs

RWE# -> WE# : DDR2 SDRAMs

RCKE0 -> CKE : DDR2 SDRAMs

RCKE1 -> CKE : DDR2 SDRAMs

RODT0 -> ODT : DDR2 SDRAMs

RODT1 -> ODT : DDR2 SDRAMs

CK0

CK0#

RESET#

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs

PCK0# -> PCK6#, PCK8#, PCK9# -> CK# : DDR2 SDRAMs

PCK7 -> CK : Register

PCK7 -> CK# : Register

** RESET#, CK AND CK# connects to both Registers. Other signals connct to one of two Registers.

NOTE: All resistor values are 22 ohms ±5% unless otherwise speciﬁed.

August 2006

Rev. 3

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

3Pages

White Electronic Designs WV3HG264M72EER-D7

ADVANCED

DDR2 ICC SPECIFICATIONS AND CONDITIONS

Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V

Symbol Parameter Condition

Operating

ICC0*

one bank

active-

tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

precharge;

Operating

one bank IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is

ICC1* active-

HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;

read- Data bus inputs are SWITCHING; Data pattern is same as ICC4W.

precharge;

ICC2P**

Precharge

power-

down

current;

All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

ICC2Q**

Precharge

quite

standby

current;

All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

ICC2N**

Precharge

standby

current;

All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus

inputs are STABLE; Data bus inputs are SWITCHING

ICC3P**

Active

power-

down

current;

All banks open; tCK = tCK(ICC), CKE is LOW; Other control

and address bus inputs are STABLE; Data bus inputs are

FLOATING

Fast PDN Exit

MRS(12) = 0

Slow PDN Exit

MRS(12) = 1

ICC3N**

Active

standby

current;

All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS#

is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

Operating All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC);

wwICCw4W.D* atabSurhset werti4teU.cotRmC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands;

current; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

ICC4R*

Operating

burst read

current;

All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0;

tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between

valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W.

Burst auto tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH

ICC5** refresh

between valid commands; Other control and address bus inputs are SWITCHING;

current; Data bus inputs are SWITCHING

Self

ICC6** refresh

current;

CK and CK# at 0V; CKE < 0.2V; Other control and address bus

inputs are FLOATING; Data bus inputs are FLOATING

Normal

ICC7*

Operating

bank

interleave

read

current;

All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(ICC) - 1*tCK(ICC);

tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH

between valid commands; Address bus inputs are STABLE during DESELECTs; Data

bus inputs are SWITCHING

806

TBD

Notes:

ICC speciﬁcation is based on SAMSUNG components. Other DRAM manufacturers speciﬁcation may be different.

* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.

** Value calculated reﬂects all module ranks in this operating condition.

665 534 403

1337 1292 1292

1472 1427 1427

644 644 644

1130 1040 1040

1220 1130 1130

1040 1040 1040

716 716 716

1490 1400 1400

1832 1652 1562

1877 1697 1562

3200 3020 3020

144 144 144

2552 2552 2552

Unit

August 2006

Rev. 3

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page

合計 : 11 ページ

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部品番号	部品説明	メーカ
WV3HG264M72EER-D7	1GB - 2x64Mx72 DDR2 SDRAM REGISTERED	White Electronic Designs

www.DataSheet.jp

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