WV3HG2256M72AER-D6 の電気的特性と機能

WV3HG2256M72AER-D6のメーカーはWhite Electronic Designsです、この部品の機能は「4GB - 2x256Mx72 DDR2 SDRAM RDIM」です。

製品の詳細 ( Datasheet PDF )

部品番号
WV3HG2256M72AER-D6

部品説明
4GB - 2x256Mx72 DDR2 SDRAM RDIM

メーカ
White Electronic Designs

ロゴ

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WV3HG2256M72AER-D6 Datasheet, WV3HG2256M72AER-D6 PDF,ピン配置, 機能

White Electronic Designs WV3HG2256M72AER-D6

ADVANCED*

4GB – 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL

FEATURES

240-pin, dual in-line memory module (DIMM)

Fast data transfer rates: PC2-6400*, PC2-5300*,

PC2-4300 and PC2-3200

Support ECC error detection and correction

VCC = VCCQ = 1.8V± 0.1V

VCCSPD = +1.7V to +3.6V

JEDEC standard 1.8V I/O (SSTL_18-compatible)

Differential data strobe (DQS, DQS#) option

Four-bit prefetch architecture

DLL to align DQ and DQS transitions with CK

Multiple internal device banks for concurrent

operation

Supports duplicate output strobe (RDQS/RDQS#)

Programmable CAS# latency (CL): 3, 4, 5* and 6*

Adjustable data-output drive strength

On-die termination (ODT)

Serial Presence Detect (SPD) with EEPROM

Auto & self refresh: 64ms 8,192 cycle refresh

Gold edge contacts

RoHS compliant

wwwD.Duaatal SRhaenekt4U.com

Package option

• 240 Pin DIMM

• PCB –30.00mm (1.181") TYP

DESCRIPTION

The WV3HG2256M72AER is a 2x256Mx72 Double Data

Rate DDR2 SDRAM high density module based on 1Gb

DDR2 SDRAM components. This memory module consists

of eighteen stacks of 256Mx4 bit with 8 banks DDR2

Synchronous DRAMs in FBGA packages, two - 14 bit

registered buffers in BGA packages mounted on a 240-pin

DIMM FR4 substrate.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

NOTE: Consult factory for availability of:

• Vendor source control options

• Industrial temperature option

Clock Speed

CL-tRCD-tRP

* Consult factory for availability

PC2-3200

200MHz

3-3-3

OPERATING FREQUENCIES

PC2-4300

266MHz

4-4-4

PC2-5300*

333MHz

5-5-5

PC2-6400*

400MHz

6-6-6

April 2006

Rev. 1

1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page

White Electronic Designs WV3HG2256M72AER-D6

ADVANCED

FUNCTIONAL BLOCK DIAGRAM

VSS

RCS1#

RCS0#

DQS0

DQS0#

DQ0

DQ1

DQ2

DQ3

DQS1

DQS1#

DQ8

DQ9

DQ10

DQ11

DQS2

DQS2#

DQ16

DQ17

DQ18

DQ19

DQS3

DQS3#

DQ24

DQ25

DQ26

DQ27

DQS4

DQS4#

DQ32

DQ33

DQ34

DQ35

DQS5

DQS5#

DQ40

DQ41

DQ42

DQ43

DQS6

DQS6#

DQ48

DQ49

DQ50

DQ51

DQS#7

DQS7#

DQ56

www.DataSheet4U.comDDQQ5578

DQ59

DQS8

DQS8#

CB0

CB1

CB2

CB3

CS0#

CS1#

BA0-BA2

A0-A13

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#**

PCK7**

PCK7#**

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

1:2

RST#

RCS0# CS# : DDR2 SDRAMs

RCS1# CS# : DDR2 SDRAMs

RBA0-RBA2 BA0-BA2 : DDR2 SDRAMs

RA0-RA13 A0-A13 : DDR2 SDRAMs

RRAS# RAS# : DDR2 SDRAMs

RCAS# CAS# : DDR2 SDRAMs

RWE# WE# : DDR2 SDRAMs SCL

RCKE0 CKE : DDR2 SDRAMs

RCKE1 CKE : DDR2 SDRAMs

RODT0 ODT : DDR2 SDRAMs

RODT1 ODT : DDR2 SDRAMs

CK0

CK0#

RESET#**

DM0/DQS9

NC/DQS9#

DQ4

DQ5

DQ6

DQ7

DM1/DQS10

NC/DQS10#

DQ12

DQ13

DQ14

DQ15

DM2/DQS11

NC/DQS11#

DQ20

DQ21

DQ22

DQ23

DM3/DQS12

NC/DQS12#

DQ28

DQ29

DQ30

DQ31

DM4/DQS13

NC/DQS13#

DQ36

DQ37

DQ38

DQ39

DM5/DQS14

NC/DQS14#

DQ44

DQ45

DQ46

DQ47

DM6/DQS15

NC/DQS15#

DQ52

DQ53

DQ54

DQ55

DM7/DQS16

NC/DQS16#

DQ60

DQ61

DQ62

DQ63

DM8/DQS17

NC/DQS17#

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

VCCSPD

I/O 0

I/O 1

I/O 2

I/O 3

CS# DQS DQS#

Serial PD

VCC/VCCQ

DDR2 SDRAMs

VREF

DDR2 SDRAMs

Serial PD

WP A0 A1 A2

VSS

SDA

DDR2 SDRAMs

SA0 SA1 SA2

PCK0-PCK6, PCK8, PCK9 CK : DDR2 SDRAMs

PCK0#-PCK6#, PCK8#, PCK9#

PCK7 CK : Register

PCK7# CK# : Register

CK# : DDR2 SDRAMs

NOTE: All resistor values are 22 ohms unless otherwise speciﬁed.

** RESET#, PCK7 and PCK7# connect to both registers. Other signals connect to one of two registers.

April 2006

Rev. 1

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

3Pages

White Electronic Designs WV3HG2256M72AER-D6

ADVANCED

DDR2 ICC SPECIFICATIONS AND CONDITIONS

VCC = +1.8V ± 0.1V

Symbol Proposed Conditions

806

Operating one bank active-precharge current;

ICC0* tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

Operating one bank active-read-precharge current;

ICC1*

IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD =

tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;

Data pattern is same as ICC4W

Precharge power-down current;

ICC2P** All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

Precharge quiet standby current;

ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

TBD

Precharge standby current;

ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

TBD

Active power-down current;

ICC3P** All banks open; tCK = tCK(ICC); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

Slow PDN Exit MRS(12) = 1

TBD

ICC3N**

Active standby current;

All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

TBD

Operating burst write current;

ICC4W*

All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =

tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs

www.DaatareSShWeeITtC4HUI.NcGo;mData bus inputs are SWITCHING

ICC4R*

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =

tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs

are SWITCHING; Data pattern is same as ICC4W

Burst auto refresh current;

ICC5B** tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

Self refresh current;

ICC6**

CK and CK# at 0V; CKE 0.2V; Other control and address bus

inputs

are FLOATING; Data bus inputs are FLOATING

Normal

TBD

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),

ICC7* tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the

following page for detailed timing conditions

TBD

Note:

ICC specs are based on SAMSUNG components. Other DRAM manufacturers parameters may be different.

* Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode.

665 534 403 Units

2,336 2,246 2,156 mA

2,516 2,426 2,336 mA

932 932 932 mA

1,940 1,760 1,760 mA

2,120 1,940 1,940 mA

1,580 1,400 1,400

932 932 932

2,300 2,120 2,120 mA

3,056 2,876 2,516 mA

8,420 8,240 8,060 mA

360 360 360 mA

6,116 5,756 5,396 mA

April 2006

Rev. 1

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page

合計 : 12 ページ

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部品番号	部品説明	メーカ
WV3HG2256M72AER-D6	4GB - 2x256Mx72 DDR2 SDRAM RDIM	White Electronic Designs

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