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WV3EG32M64ETSU-D3 の電気的特性と機能
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WV3EG32M64ETSU-D3のメーカーはWhite Electronic Designsです、この部品の機能は「256MB - 32Mx64 DDR SDRAM UNBUFFERED」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 WV3EG32M64ETSU-D3 |
| 部品説明 256MB - 32Mx64 DDR SDRAM UNBUFFERED |
| メーカ White Electronic Designs |
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このページの下部にプレビューとWV3EG32M64ETSU-D3ダウンロード（pdfファイル）リンクがあります。 Total 12 pages |
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White Electronic Designs
WV3EG32M64ETSU-D3
ADVANCED*
256MB – 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
• VCC = VCCQ = +2.5V ±0.2V
184 pin DIMM package
• D3 PCB height: 28.58mm (1.125")
DESCRIPTION
The WV3EG32M64ETSU is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
July 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 Page
White Electronic Designs
WV3EG32M64ETSU-D3
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
www.DataSheet4U.com
CS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS#
CAS#
BA0-BA1
WE#
A0-A12
CKE0
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE#: DDR SDRAMs
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
SERIAL PD
SCL SDA
WP A0 A1 A2
SA0 SA1 SA2
CLOCK INPUT
CK0, CK0#
2 SDRAMS
CK1, CK1#
3 SDRAMS
CK2, CK2#
3 SDRAMS
VCCSPD
VCC/VCCQ
VREF
VSS
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
*Clock Net Wiring
R = 120 Ohm
Card
Edge
DRAM 1
1.5PF
DRAM 3
1.5PF
1.5PF
DRAM 5
1.5PF
NOTE: All datalines are terminated through a 22 ohm series resistor.
July 2005
Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
3Pages
White Electronic Designs
WV3EG32M64ETSU-D3
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4. Timing Patterns :
• DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
• DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
www.DataSheet4U.com
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
July 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
6 Page
合計 : 12 ページ |
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| 部品番号 | 部品説明 | メーカ |
| WV3EG32M64ETSU-D3 | 256MB - 32Mx64 DDR SDRAM UNBUFFERED | White Electronic Designs |