WV3EG264M64EFSU-D4 の電気的特性と機能

WV3EG264M64EFSU-D4のメーカーはWhite Electronic Designsです、この部品の機能は「1GB - 2x64Mx64 DDR SDRAM UNBUFFERED」です。

製品の詳細 ( Datasheet PDF )

部品番号
WV3EG264M64EFSU-D4

部品説明
1GB - 2x64Mx64 DDR SDRAM UNBUFFERED

メーカ
White Electronic Designs

ロゴ

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WV3EG264M64EFSU-D4 Datasheet, WV3EG264M64EFSU-D4 PDF,ピン配置, 機能

White Electronic Designs WV3EG264M64EFSU-D4

PRELIMINARY*

1GB – 2x64Mx64 DDR SDRAM UNBUFFERED

FEATURES

PC2700 @ CL2.5

Double-data-rate architecture

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Auto and self refresh, (8K/64ms refresh)

Serial presence detect

Power supply: VCC/VCCQ: 2.5V ± 0.2V

Dual Rank

Standard 200 pin SO-DIMM package

• Package height options:

D4: 31.75 mm (1.25”)

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

DESCRIPTION

The WV3EG264M64EFSU is a 2x64Mx64 Double Data

Rate SDRAM memory module based on 512Mb DDR

SDRAM component. The module consists of sixteen

64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages

mounted on a 200 pin FR4 substrate.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

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OPERATING FREQUENCIES

Clock Speed

CL-tRCD-tRP

DDR333 @CL=2.5

166MHz

2.5-3-3

August 2005

Rev. 0

1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page

White Electronic Designs WV3EG264M64EFSU-D4

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

CS1#

CS0#

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

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DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S0#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS S1#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

BA0-BA1

A0-A12

RAS#

CAS#

WE#

CKE0

CKE1

VCCSPD

VCC/VCCQ

VREF

VSS

DDR SDRAMs

SPD

DDR SDRAMs

Clock Wiring

Clock

Input

SDRAMs

CK0/CK0#

CK1/CK1#

8 SDRAMs

SERIAL PD

SCL

SDA

WP A0 A1 A2

SA0 SA1 SA2

NOTE: All datalines are terminated through a 22 ohm series resistor

August 2005

Rev. 0

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

3Pages

White Electronic Designs WV3EG264M64EFSU-D4

PRELIMINARY

Parameter

Symbol

IDD SPECIFICATIONS AND TEST CONDITIONS

0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V

Conditions

Operating current

One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN);

IDD0* DQ, DM and DQS inputs change once per clock cycle; Address and control

inputs change once every two clock cycles

Operating current

IDD1*

One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN);

IOUT = 0mA; Address and control inputs change once per clock cycle

Percharge power-

down standby current

IDD2P**

All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW

Idle standby current

IDD2F**

CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address

and other control inputs changing once per clock cycle. VIN = VREF for DQ,

DQS and DM

Active power-down

standby current

IDD3P**

One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW

Active standby

current

IDD3N**

CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX);

tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address

and other control inputs changing once per clock cycle

Operating current

IDD4R*

Burst = 2; Reads; Continuous burst; One device bank active; Address and

other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA

Operating current

IDD4W*

Burst = 2; Writes; Continuous burst; One device bank active; Address and

other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and

DQS inputs change twice per clock cycle

Auto refresh current

IDD5**

tRC = tRFC(MIN)

Self refresh current

IDD6**

CKE < 0.2V

Orerating current

IDD7A*

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Four device bank interleaving Reads Burst = 4 with auto precharge;

tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during

Active READ, or WRITE commands

NOTE:

IDD speciﬁcation is based on Micron components. Other DRAM Manufacturers speciﬁcation may be different.

* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.

** Value calculated as all module ranks in this operation condition.

DDR333 @

CL = 2.5 Max

1080

1320

720

560

800

1360

1440

4640

3280

Unit

August 2005

Rev. 0

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page

合計 : 11 ページ

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部品番号	部品説明	メーカ
WV3EG264M64EFSU-D4	1GB - 2x64Mx64 DDR SDRAM UNBUFFERED	White Electronic Designs

www.DataSheet.jp

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