• Eight 100 BASE-TX/FX ports; each port individually
configurable to TX or FX
• Direct interface with analog clock generation/recov-
• Three Media Independent Interface (MII)
• Expandable to increase number of repeater ports
• Low latency design simplified high port number Class
II repeater implementation
• Management features accessible through MII or se-
• All ports can be separately isolated or partitioned in
reponse to fault conditions
• Conforms to IEEE 802.3u Repeater Unit Specifica-
• LED display for TX/FX port activities and collisions
• 208-pin, CMOS device in PQFP package
2.0 GENERAL DESCRIPTION
The MX98741 (100BASE-TX Repeater Controller, XRC)
is a 208-pin PQFP device that interfaces directly with
offshell clock generation/recovery chips. Eight ports can
be configured as 100 BASE-TX or FX ports individually.
Three additional ports have Media Independent Inter-
faces (MII) which allow easy connection of management
and bridge devices. The expansion port allows multiple
XRCs to be linked together to form a repeater of high
port counts. LEDs are provided for visual monitoring of
TX/FX port activities and collisions.
The XRC's design inserts minimum delay between the
TX/FX ports and the expansion port. A master-slave
type arbitration is also implemented to shorten the
communciation time among multiple XRCs. As a re-
sult, design for Class II stackable hub is greatly simpli-
Control Functions and management status are imple-
mented through internal registers. These registers are
accessed via either standard MII management interface
(MDC, MDIO) or several serial ports. These serial ports
are accessed easily by hardware for debugging and
configuration purposes. A dedicated management chip
can also utilize these serial ports to access the XRC.
REV. 1.4, NOV. 07, 1998
4.0 PIN DESCRIPTION
Table 4-1 Pin Description for MX98741
A. MX Data Transceiver (Am78965/Am78966 or MC68836), 98 pins
TDAT[0:7][0:4] O, EXP Transmit Data. These five outputs are 4B/5B encoded transmit
data symbols, driven at the rising edge of TXCLK.
TDAT4 is the Most Significant Bit.
Transmit Clock. This pin supplies the frequency reference to the
transmit logic. It should be driven by an external 25 MHz
crystal-controlled clock source.
Receive Data. These 5-bit parallel data symbols from transceiver
are latched by the rising edge of RSCLK.
RDAT4 is the Most Significant Bit.
Recovered Sumbol Clock. This is a 25 MHz clock, which is derived
from the clock synchroniztion PLL circuit.
Signal Detect. This signal indicates that the received signal is above
the detection threshold and will be used for the link test state
I, TTL Core Clock. 50M Clock input used by Repeater Core.
REV. 1.4, NOV. 07, 1996
E. LED Pins, 9 pins
O, TTL Activity LED. Active Low. This pin provides a minimum 80ms ON
time (low) and 20ms OFF time (high) for activities on each port.
External buffers are necessary to drive LEDs.
O, MII Collision LED. This pin is capable of driving LED directly to display
Activity status. The ON (active low) time and OFF (active high)
time of LED's is 80ms and 20ms respectively.
F. Media Independent Interface (MII), 33 pins
I, TTL Transmit Enable MII A. Synchronous to the TXCLK's rising edge. It
is asserted by the MAC with the first nibble of the preamble and
remains asserted while all nibbles to be transmitted are presented.
I, TTL Transmit Data MII A. Synchronous to the TXCLK's rising edge. For
each TXCLK period in which TXENA is asserted, TXDA[3:0] are
also driven by the MAC. While TXENA is de-asserted, the value of
TXDA[3:0] is ignored. TXDA3 is the Most Significant Bit.
I, TTL Transmit Error MII A. Synchronous to the TXCLK's rising edge.
When TXERA is asserted for one or more TXCLK period while
TXENA is also asserted, one or more "HALT" symbols will present
O, TTL Receive Data Valid MII A. Synchronous to RXCLK's rising edge.
This signal remains asserted through the whole frame, starting with
the start-of-frame delimiter and excluding any end-of-frame delim-
iter. High impedance after reset.
O, TTL Carrier Sense MII A. In TX mode, synchronous to RXCLK. This
pin is asserted when (1) the receiving medium is not idle, or (2) the
transmitting medium is not idle in the half-duplex mode. High im-
pedance after reset.
I/O, TTL Management Data Input/Output. A bi-directional signal. After re-
set, this pin is in high-impedance state. The selection of input/
output direction is based on IEEE 802.3u management functions
(Section 22.2.4). Low after reset due to internally pull-down. When
RDXWR is low (i.e. Write operation, MDIO will be forced to low to
disable the function of MDC and MDIO. i.e. Programming internal
registers through register access pins owns higher priority.
REV. 1.4, NOV. 07, 1996