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MX98726EC の電気的特性と機能
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MX98726ECのメーカーはMacronix Internationalです、この部品の機能は「SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 MX98726EC |
| 部品説明 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER |
| メーカ Macronix International |
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www.DataSheet4U.com
MX98726EC
SINGLE CHIP 10/100 FAST ETHERNET
CONTROLLER WITH uP INTERFACE
1.0 Features
• Direct interface to 80188/186 up to 40Mhz.
• Integrated 10/100 TP tranceiver on chip to reduce
overall cost
• Optional MII interface for external tranceiver.
• Fully comply to IEEE 802.3u spec.
• Best fit in network printer and hub/switch manage-
ment application
• A local DMA channel between on-chip FIFOs and
packet memory
• Shared memory architecture allow host and
MX98726EC to use only one single SRAM
• Host DMA can share packet memory with local DMA
with simple hand shake protocol for x188/186 type of
processor
• Supports proprietary local DMA channel to share
packet memory
• Support bus size configuration:
- CPU : 8 bits, SRAM: 8 bits
- CPU : 16 bits, SRAM: 8/16 bits
• Flexible packet buffer partition and addressing space
for 32k, 64k up to 512K bytes
• NWAY autonegotiation function to automatically set
up network speed and protocol
• 3 loop back modes for system level diagnostics
• Rich on-chip register set to support a wide variety of
network management functions
• Support 64 bits hash table for multicast addressing
• Support software EEPROM interface for easy up-
grade of EEPROM content
• Support 1K bits and 4K bits EEPROM interface
• 5V CMOS in 128 PQFP package for minimum board
size application
1.1 Introduction
MX98726EC ( Generic MAC , or GMAC ) is a cost effec-
tive solution as a generic single chip 10/100 Fast Ethernet
controller. It is designed to directly interface 80188, 80186
( host ) without glue logic.Two types of memory sharing
schemes are supported, i.e.interleaved and shared mode
to support a variety of applications. Single chip solution
will help reduce system cost not only on the compo-
nents but also the board size. Full NWAY function with
10/100 tranceiver will ease the field installation, simply
plug the chip in and it will connect itself with the best
protocol available.
The interleaved mode allow uP to access SRAM (
packet/host buffer ) through MX98726EC's local DMA
channel. This way, no extra SRAM interface logic is
needed on the host side. If high performance is desired,
then shared memory mode is another alternative which
allow host to access SRAM on its own by denying SRAM
bus grant to MX98726EC using simple hand shake pro-
tocol. Without SRAM bus grant, MX98726EC will float
its interface connected to the SRAM, therefore host can
utilize its own memory subsystem to conduct its own
SRAM access.
A intelligent built-in SRAM bus arbitor will manage all
the SRAM access requests from host, on-chip transmit
channel and on-chip receive channel. The throughput
of these network channels and MX98726EC's DMA burst
length can be easily adjusted by option bits on the chip.
These options can help system developers to "fine tune"
a best cost/performance ratio.
MX98726EC is also equipped with fast back-to-back
transmit capability which allow software to "fire" as many
transmit packets as needed in a single command. Re-
ceive FIFO also allow back-to-back reception. Optional
EEPROM can be used to stored network network ad-
dress and other information. In case cost is really a con-
cern, most configuration options including network ad-
dress can be programmed through uP.
P/N:PM0729
REV. 1.1, MAY. 28, 2001
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1 Page
www.DataSheet4U.com
MX98726EC
Host Memory
Subsystem
Packet
buffer
SRAM Bus
EPROM
C46/C66
uP with
shared bus
HOLD
HLDA
MX98726EC
RJ45 TP cable
Xformer
CSB
Decode
Customer Application
Shared memory Architecture
1.4 Combo Application
Customer Application
Host Memory
Subsystem
Host
Packet
buffer
EPROM
C46/C66
Local DMA
CSB
MX98726EC
or
1M 8PHY
or
10M 8PHY
Decode
COMBO APPLICATION
RJ11 Phone Line
Xformer
RJ45 TP Cable
Xformer
P/N:PM0729
REV. 1.1, MAY. 28, 2001
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3Pages
www.DataSheet4U.com
MX98726EC
45 HOLD
O, 4ma Packet Memory Bus Hold Request : Active high to request Host to "float"
its interface of the packet memory. Host grants the packet buffer bus to
MX98726EC by asserting HLDA = 1.
46 HLDA
I, TTL
Packet Memory Bus Hold Acknowledge: Packet buffer bus is granted to
MX98726EC. If HLDA=0 then MX98726EC will float its interface on the
packet buffer. Internal pull-up.
77
PSENB
I, TTL
Host Program Strobe Enable : Active low to indicate current cycle is a
ROM access and MX98726EC will not decode this ROM cycle. PSENB
must high for packet memory access. Internal pull-up.
74 RSTB
I,TTL
Host Reset Input : Active low, Schmitt trigger input, Internal pull-up.
Packet Buffer Interface :
PIN# Pin Name
1, MA[19:3]
115-119
7 MA19(RXD0)
Type
O,4ma
I/O, 4ma
6 MA18(RXD1) I/O, 4ma
5 MA17(RXD2) I/O, 4ma
4 MA16(RXD3) I/O, 4ma
90-96, MD[15:0]
98-104,
106-109
114 MA2(EEDO)
I/O,4ma
1/O,4ma
113 MA1(EEDI) 1/O,4ma
111 MA0(EECK) 1/O,4ma
87
86
88, 89
MOEB
MCSB
MWEB[1:0]
O,4ma
O,4ma
O,4ma
P/N:PM0729
Description
Memory Address Bit 19-0: If HLDA = 0 then all these address lines are tri-
stated.
Memory Address Bit19, when on-chip tranceiver is used, it is defined as
MA19, while in MII mode, it is used as receive data bit RXD0 pin.
Memory Address Bit18, when on-chip tranceiver is used, it is defined as
MA18, while in MII mode, it is used as receive data bit RXD1 pin.
Memory Address Bit17, when on-chip tranceiver is used, it is defined as
MA17, while in MII mode, it is used as receive data bit RXD2 pin.
Memory Address Bit16, when on-chip tranceiver is used, it is defined as
MA16, while in MII mode, it is used as receive data bit RXD3 pin.
Memory Data Bit 15-0 : Internal pull-down.
Memory Address Bit 2 or EEPROM Data Out bit: Right after host reset,
GMAC automatically load configuration information from external EEPROM.
During this period, MA2 pin acts as a EEDO pin that read in output data
stream from EEPROM. After EEPROM auto load sequence is done, this
pin becomes MA2 together with MA[19:3] forms packet buffer address
line 19 - 0. Internally pull-down.
Memory Address Bit 1 or EEPROM Data In bit: During EEPROM auto load
sequence, MA1 pin acts as EEDI pin that write data stream into EEPROM.
After EEPROM auto load sequence is done, this pin becomes MA1, to-
gether with MA[19:2] forms packet buffer address lines.
Memory Address Bit 0 or EEPROM Clock Input : During EEPROM auto
load sequence, MA0 pin acts as EECK pin that provides clock to EEPROM.
After EEPROM auto load sequence is done, this pin becomes MA0, to-
gether with MA[19:1] forms packet buffer address lines.
Memory Output Enable: Active low during packet buffer read access.
Memory Chip Select: Active low during packet buffer accesses.
Byte Write Enable: Active low during packet buffer write cycle. MWEB1 for
high byte and MWEB0 for low byte.
REV. 1.1, MAY. 28, 2001
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6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| MX98726EC | SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER | Macronix International |