|
74AS244 の電気的特性と機能
|
74AS244のメーカーはFairchild Semiconductorです、この部品の機能は「DM74AS244」です。 |
|
|
製品の詳細 ( Datasheet PDF )
| 部品番号 74AS244 |
| 部品説明 DM74AS244 |
| メーカ Fairchild Semiconductor |
ロゴ |
このページの下部にプレビューと74AS244ダウンロード（pdfファイル）リンクがあります。 Total 5 pages |
No Preview Available ! |
www.DataSheet4U.com
October 1986
Revised March 2000
DM74AS240 • DM74AS244
3-STATE Bus Driver/Receiver
General Description
This family of Advance Schottky 3-STATE Bus circuits are
designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communi-
cation Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated trans-
mission lines down to 133Ω. The input characteristics of
the circuits likewise have a high impedance so it will not
significantly load the transmission line. The package con-
tains eight 3-STATE buffers organized with four buffers
having a common 3-STATE enable gate. The DM74AS240
and DM74AS244 are eight wide in a 20 pin package, and
may be used as a 4 wide bidirectional or eight wide unidi-
rectional. The buffer selection includes inverting and non-
inverting, with enable or disable 3-STATE control.
Features
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Improved switching performance with less power dissi-
pation compared with Schottky counterpart
s Functional and pin compatible with 74LS and Schottky
counterpart
s Switching response specified into 500Ω and 50 pF
s Specified to interface with CMOS at VOH = VCC − 2V
Ordering Code:
Order Number Package Number
Package Description
DM74AS240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS240N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74AS244WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS244N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74AS240
DM74AS244
Function Tables
DM74AS240
Inputs
GA
LL
LH
HX
L = LOW Logic Level
Output
Y
H
L
Z
H = HIGH Logic Level
DM74AS244
Inputs
Output
GA
LL
LH
HX
Y
L
H
Z
X = Either LOW or HIGH Logic Level Z = High Impedance
© 2000 Fairchild Semiconductor Corporation DS006298
www.fairchildsemi.com
1 Page
www.DataSheet4U.com
DM74AS240 Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
R1 = R2 = 500Ω
CL = 50 pF
tPZL Output Enable to LOW Level
tPZH Output Enable to HIGH Level
tPLZ Output Disable from LOW Level
tPHZ Output Disable from HIGH Level
DM74AS244 Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
R1 = R2 = 500Ω
CL = 50 pF
tPZL Output Enable to LOW Level
tPZH Output Enable to HIGH Level
tPLZ Output Disable from LOW Level
tPHZ Output Disable from HIGH Level
From
(Input)
A
To
(Output)
Y
Min
2
A Y2
G Y2
G Y2
G Y2
G Y2
Max
6.5
5.7
9
6.4
9.5
5
Units
ns
ns
ns
ns
ns
ns
From
(Input)
A
To
(Output)
Y
Min
2
A Y2
G Y2
G Y2
G Y2
G Y2
Max
6.2
6.2
7.5
9
9
6
Units
ns
ns
ns
ns
ns
ns
3 www.fairchildsemi.com
3Pages
合計 : 5 ページ |
| PDF ダウンロード [ 74AS244 データシート.PDF ] |
|
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
|
|
| 部品番号 | 部品説明 | メーカ |
| 74AS243 | DM74AS243 |  ETC |
| 74AS244 | DM74AS244 | Fairchild Semiconductor |