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STAC9753 の電気的特性と機能
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STAC9753のメーカーはIDTです、この部品の機能は「(STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 STAC9753 |
| 部品説明 (STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS |
| メーカ IDT |
ロゴ |
このページの下部にプレビューとSTAC9753ダウンロード（pdfファイル）リンクがあります。 Total 70 pages |
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DATASHEET
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE STAC9752/9753
DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Description
IDT's STAC9752/9753 are general purpose 20-bit, full
duplex, audio CODECs conforming to the analog
component specification of AC'97 (Audio CODEC 97
Component Specification Rev. 2.3). The STAC9752/9753
incorporate IDT's proprietary Σ∆ technology to achieve a
DAC SNR in excess of 90dB. The DACs, ADCs and mixer
are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs,
two stereo outputs, and one mono output channel. The
STAC9752/9753 include digital output capability for support
of modern PC systems with an output that supports the
SPDIF format. The STAC9752/9753 are standard
2-channel stereo CODECs. With IDT’s headphone
capability, headphones can be driven without an external
amplifier. The STAC9752/9753 may be used as a
secondary or tertiary CODECs, with STAC9700/21/44/56/
08/84/50/66 as the primary, in a multiple CODEC
configuration conforming to the AC'97 Rev. 2.3
specification. This configuration can provide the true
six-channel, AC-3 playback required for DVD applications.
The STAC9752/9753 communicate via the five AC-Link
lines to any digital component of AC'97, providing flexibility
in the audio system design. Packaged in an AC'97
compliant 48-pin TQFP, the STAC9752/9753 can be placed
on the motherboard, daughter boards, PCI, AMR, CNR,
MDC or ACR cards.
Features
• High performance Σ∆ technology
• AC’97 Rev 2.3 compliant
• 20-bit full duplex stereo ADCs, DACs
• Independent sample rates for ADCs & DACs
• 5-wire AC-Link protocol compliance
• 20-bit SPDIF Output
• Internal Jack Sensing on Headphone and Line_Out
• Internal Microphone Input Sensing
• Digital PC Beep Option
• Extended AC’97 2.3 Paging Registers
• Adjustable VREF amplifier
• Digital-ready status
• General purpose I/Os
• Crystal Elimination Circuit
• Headphone drive capability (50 mW)
• 0dB, 10dB, 20dB, and 30dB microphone boost
capability
• +3.3 V (STAC9753) and +5 V (STAC9752) analog
power supply options
• Pin compatible with the STAC9700, STAC9721,
STAC9756
• 100% pin compatible with STAC9750 and
STAC9766
• IDT Surround (SS3D) Stereo Enhancement
• Energy saving dynamic power modes
• Multi-CODEC option (Intel AC'97 rev 2.3)
• Six analog line-level inputs
• 90dB SNR Line to Line
• SNR > 89dB through Mixer and DAC
IDT™
1 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
V 3.3 101006
1 Page
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
5.3.8. Slot 12: Audio GPIO Control Channel ............................................................................... 36
5.4. AC-Link Input Frame (SDATA_IN) ................................................................................................. 36
5.4.1. Slot 0: TAG ........................................................................................................................37
5.4.2. Slot 1: Status Address Port / SLOTREQ signalling bits .....................................................37
5.4.3. Slot 2: Status Data Port ..................................................................................................... 38
5.4.4. Slot 3: PCM Record Left Channel ..................................................................................... 38
5.4.5. Slot 4: PCM Record Right Channel ................................................................................... 38
5.4.6. Slot 5: Modem Line 1 ADC ................................................................................................ 38
5.4.7. Slot 6 - 9: ADC ................................................................................................................... 38
5.4.8. Slots 7 & 8: Vendor Reserved ........................................................................................... 39
5.4.9. Slot 10 & 11: ADC ............................................................................................................. 39
5.4.10. Slot 12: Reserved ............................................................................................................ 39
5.5. AC-Link Interoperability Requirements and Recommendations ...................................................... 40
5.5.1. “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data ...............................................40
5.6. Slot Assignments for Audio ............................................................................................................. 41
6. STAC9752/9753 MIXER ..........................................................................................................43
7. MIXER FUNCTIONAL DIAGRAMS ........................................................................................44
7.1. Analog Mixer Input ......................................................................................................................... 45
7.2. Mixer Analog Output ....................................................................................................................... 45
7.3. SPDIF Digital Mux ...........................................................................................................................45
7.4. PC Beep Implementation ................................................................................................................ 46
7.4.1. Analog PC Beep ................................................................................................................ 46
7.4.2. Digital PC Beep ................................................................................................................. 46
8. PROGRAMMING REGISTERS ...............................................................................................47
8.1. Register Descriptions ...................................................................................................................... 48
8.1.1. Reset (00h) ....................................................................................................................... 48
8.1.2. Master Volume Registers (02h) ........................................................................................ 48
8.1.3. Headphone Volume Registers (04h) ................................................................................. 49
8.1.4. Master Volume MONO (06h) ............................................................................................ 50
8.1.5. PC BEEP Volume (0Ah) ................................................................................................... 51
8.1.6. Phone Volume (Index 0Ch) .............................................................................................. 51
8.1.7. Mic Volume (Index 0Eh) .................................................................................................... 52
8.1.8. LineIn Volume (Index 10h) ............................................................................................... 52
8.1.9. CD Volume (Index 12h) .................................................................................................... 53
8.1.10. Video Volume (Index 14h) ............................................................................................. 53
8.1.11. Aux Volume (Index 16h) ................................................................................................. 54
8.1.12. PCMOut Volume (Index 18h) ......................................................................................... 54
8.1.13. Record Select (1Ah) ....................................................................................................... 55
8.1.14. Record Gain (1Ch) ......................................................................................................... 55
8.1.15. General Purpose (20h) ................................................................................................... 56
8.1.16. 3D Control (22h) ............................................................................................................. 56
8.1.17. Audio Interrupt and Paging (24h) .................................................................................... 57
8.1.18. Powerdown Ctrl/Stat (26h) .............................................................................................. 58
8.1.19. Extended Audio ID (28h) ................................................................................................ 59
8.1.20. Extended Audio Control/Status (2Ah) ............................................................................. 61
8.1.21. PCM DAC Rate Registers (2Ch and 32h) ...................................................................... 63
8.1.22. PCM DAC Rate (2Ch) .................................................................................................... 63
8.1.23. PCM LR ADC Rate (32h) ............................................................................................... 63
8.1.24. SPDIF Control (3Ah) ........................................................................................................ 64
8.2. General Purpose Input & Outputs ................................................................................................... 64
8.2.1. EAPD ................................................................................................................................. 64
8.2.2. GPIO Pin Definitions .......................................................................................................... 65
8.2.3. GPIO Pin Implementation .................................................................................................. 65
8.2.4. Extended Modem Status and Control Register (3Eh) ........................................................65
8.2.5. GPIO Pin Configuration Register (4Ch) ............................................................................. 66
IDT™
3 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
REV 3.3 1206
3Pages
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
LIST OF TABLES
Table 1. Clock Mode Configuration ............................................................................................................... 17
Table 2. Common Clocks and Sources ......................................................................................................... 18
Table 3. Recommended CODEC ID strapping ............................................................................................. 26
Table 4. AC-Link output slots (transmitted from the Controller) ..................................................................... 29
Table 5. The AC-Link input slots (transmitted from the CODEC) .................................................................. 30
Table 6. VRA Behavior .................................................................................................................................. 31
Table 7. Output Slot 0 Bit Definitions ............................................................................................................ 34
Table 8. Command Address Port Bit Assignments ........................................................................................ 35
Table 9. Status Address Port Bit Assignments .............................................................................................. 37
Table 10. Status Data Port Bit Assignments .................................................................................................. 38
Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................ 40
Table 12. Secondary CODEC Addressing: Slot 0 Tag Bits ........................................................................... 40
Table 13. AC-Link Slot Definitions ................................................................................................................. 41
Table 14. AC-Link Input Slots Dedicated To Audio ....................................................................................... 41
Table 15. Audio Interrupt Slot Definitions ...................................................................................................... 42
Table 16. Digital PC Beep Examples ............................................................................................................. 46
Table 17. Programming Registers ................................................................................................................. 47
Table 18. Extended Audio ID Register Functions .......................................................................................... 60
Table 19. AMAP compliant ............................................................................................................................ 63
Table 20. Hardware Supported Sample Rates .............................................................................................. 63
Table 21. Supported Jack and Microphone Sense Functions .......................................................................71
Table 22. Reg 68h Default Values ................................................................................................................. 73
Table 23. Gain or Attenuation Examples ....................................................................................................... 73
Table 24. Register 68h/Page 01h Bit Overview ............................................................................................. 73
Table 25. Sensed Bits (Outputs) ................................................................................................................... 75
Table 26. Sensed Bits (Inputs) ...................................................................................................................... 75
Table 27. Low Power Modes ......................................................................................................................... 80
Table 28. CODEC ID Selection .....................................................................................................................82
Table 29. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................83
Table 30. Test Mode Activation .....................................................................................................................84
Table 31. ATE Test Mode Operation ............................................................................................................. 84
Table 32. Digital Connection Signals ............................................................................................................. 86
Table 33. Analog Connection Signals ........................................................................................................... 87
Table 34. Filtering and Voltage References .................................................................................................. 88
Table 35. Power and Ground Signals ............................................................................................................ 88
IDT™
6 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
REV 3.3 1206
6 Page
合計 : 70 ページ |
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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| 部品番号 | 部品説明 | メーカ |
| STAC9750 | (STAC9750 / STAC9751) VALUE-LINE TWO-CHANNEL AC97 CODECS | IDT |
| STAC9751 | (STAC9750 / STAC9751) VALUE-LINE TWO-CHANNEL AC97 CODECS | IDT |
| STAC9752 | (STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS | IDT |
| STAC9752A | (STAC9752A / STAC9753A) AC97 2.3 CODECS | IDT |