
AN239 の電気的特性と機能
AN239のメーカーはSiliconです、この部品の機能は「Expanding ADC1 Dyanmic Range」です。 

製品の詳細 ( Datasheet PDF )
部品番号 AN239 
部品説明 Expanding ADC1 Dyanmic Range 
メーカ Silicon 
ロゴ 
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AN239
EXPANDING ADC1 DYNAMIC RANGE FOR THE Si8250
1. Introduction
The Si8250 data sheet specifies a common mode input range of 0.6 to 1.2 V for ADC1. This range effectively limits
the dynamic voltage output range in voltagecontrolled converters. For example, the output range for a 3.3 V power
supply designed to generate a 1.00 V sense would have an absolute maximum dynamic range of 1.98 to 3.96 V. In
reality, the active regulation point would need to be something greater than 1.98 V and less than 3.96 V since these
are on the very fringes of the common mode specification. If a design requires wider dynamic output voltage range
(e.g., 2.00–5.70 V) then a simple resistor divider will not work. This application note discusses a simple and
inexpensive solution to expand the dynamic range for applications such as power factor correction and wide
variable output power supplies.
2. ADC1 Common Mode Limits
The specified common mode range for ADC1 (Figure 1) is from 0.6 V to the voltage reference which is typically
1.2 V. This simply means that the input voltages to ADC1 from both VSENSE and the REFDAC should stay within
the range of 0.6 to 1.2 V referenced to the common ground to achieve good linear response. For input voltages
much lower than the common mode specification, ADC1 exhibits nonlinear characteristics. Figure 2 shows an
example of the ADC1 dc response when the inputs are significantly out of specification. For input voltages above
the common mode range the input is effectively “cut off” yielding no change in the ADC output.
VSENSE
200 kHz
12Bit
ADC
+Bits [11:6] 
+ Bits [8:3]
REFDAC0H
REFDAC0L
+
10 MHz
6Bit
 ADC
6
REFDAC
9
6
1
ADC1DAT
1
0 6 To PID Filter
2
3
PID Input
MUX
SFR Bus
READ/WRITE
REFDAC0H
REFDAC0L
Figure 1. ADC1 Block Diagram
ADC1 Output
6 mV Step, VSENSE = 301 mV, VREF = 1.226 V
32
22
12
2
8
18
28
0 50 100 150 200
REFDAC
Actual Data
Ideal Data
Figure 2. ADC1 Results Below the Common Mode Specification
Rev. 0.1 11/05
Copyright © 2005 by Silicon Laboratories
AN239
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AN239
4. Expanding the Dynamic Range
To dynamic range may be expanded by allowing the α ratio in Equation 1 and Equation 3 to be variable. This is
accomplished by changing the value of Rx in Figure 3. One solution is to connect parallel resistors to port pins on
the Si8250 as shown in Figure 5. To change the α ratio, drive one of the connected port pins low to engage a
parallel resistance or allow the pin to float (high impedance) to disengage a parallel resistance.
From filter
Vout
Rs
Vsense
P0.0
P0.1
P0.n
R2
R3
R1
Rn
Rx = R1  R2  R3  Rn
Figure 5. Feedback with Common Mode Compensation
4.1. Adding Margin to the Common Mode Limits
It is important to add margin to the common mode limits to ensure that ADC1 is not converting at the boundary of
the common mode range. Operating at the boundary ultimately affects the transient response performance. For
example, if the reference DAC shown in Figure 1 is set to deliver a 1.17 V signal to ADC1, this would leave 30 mV
operating margin for ADC1 Vs (min). In a situation where ADC1 is set to deliver a 6 mV resolution, 30 mV is only
5 LSB. Thus, if a positive going transient were to occur, the maximum possible error from ADC1 would be 5 LSBS.
Thus, the loop response is asymmetrical in this example. The bandwidth is severely limited for positive transients
(up to 5 LSB), while the bandwidth for negative going transients would be limited only by the maximum dynamic
range of ADC1 (up to 32 LSB).
Therefore, it is necessary to calculate the operating limits set by deciding the maximum allowed transient m (LSB).
The α ratios and resistor values are determined based on these operating limits. Equation 4 defines the minimum
sense voltage Vs (min) and Equation 5 defines the maximum sense voltage Vs (max). In these equations Vstep is
the resolution of ADC1 (mv), and Vcom is the common mode voltage.
Vs(min) = Vcom(min) + m(Vstep) → Vs(min) = 0.6V + m(Vstep)
Equation 4. Minimum Sense Voltage
Vs(max) = Vcom(max) – m(Vstep) → Vs(max) = 1.2V – m(Vstep)
Equation 5. Maximum Sense Voltage
Rev. 0.1
3
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4.4. Design Example
An output range from 2.0 to 5.7 V is desired for a particular power supply (this example is used quite often
throughout this application note). The highside margin is specified to be 32 LSB, and the lowside margin is
specified to be 16 LSB. The ADC resolution is set at 4 mV. These settings yield a sense voltage range of 0.664 to
1.072 V. The highside resistor, Rs, is specified to be 7500 Ω. The results are easily calculated with a spreadsheet
and are shown in Figure 7. The resulting circuit is shown in Figure 8.
Parameter
Vout(min)
Vcom(min)
Vcom(max)
Low offset
High offset
Step size
Rs
Vs(min)
Vs(max)
Value
2.00
0.60
1.20
16
32
0.004
7500
0.664
1.072
Unit
V
V
V
LSB
LSB
V
ohms
V
V
n αn
Vn
Rxn
Rn
1 3.01 3.23 3727.54 3727.54
2 4.86 5.21 1941.58 4052.35
3 7.85 8.42 1094.76 2510.04
4 12.67 13.59 642.41 1554.73
5 20.46 21.94 385.35 963.00
6 33.04 35.42 234.11 596.49
7 53.34 57.18 143.30 369.47
Figure 7. Example Spreadsheet Calculations for a Wide Dynamic Output
The Power
VIN Stage and Filter
7.5k
Rs
VOUT
VSENSE
Si8250 P0.0
P0.1
4.05k
2.51k
R2
R3
3.73k
R1
Figure 8. The Example Voltage Sense Circuit
6 Rev. 0.1
6 Page
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