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XC2V4000のメーカーはXilinxです、この部品の機能は「(XC2Vxxx) Virtex-II Platform FPGAs: Complete Data Sheet」です。


製品の詳細 ( Datasheet PDF )

部品番号
XC2V4000
部品説明
(XC2Vxxx) Virtex-II Platform FPGAs: Complete Data Sheet
メーカ
Xilinx
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XC2V4000 Datasheet, XC2V4000 PDF,ピン配置, 機能
0
R Virtex™-II Platform FPGAs:
Complete Data Sheet
DS031 August 1, 2003
0 0 Product Specification
This document includes all four modules of the Virtex-II Platform FPGA data sheet.
Module 1:
Introduction and Overview
DS031-1 (v2.0) August 1, 2003
7 pages
• Summary of Features
• General Description
• Device/Package Combinations and Maximum I/O
• Ordering Information
Module 2:
Functional Description
DS031-2 (v3.0) August 1, 2003
40 pages
• Detailed Description
• Digitally Controlled Impedance (DCI)
• Configurable Logic Blocks (CLBs)
• Sum of Products
• 3-State Buffers
• 18-Kb Block SelectRAM™ Resources
• 18-Bit x 18-Bit Multipliers
• Global Clock Multiplexer Buffers
• Digital Clock Manager (DCM)
• Active Interconnect Technology
• Creating a Design
• Configuration
Module 3:
DC and Switching Characteristics
DS031-3 (v3.0) August 1, 2003
38 pages
• Electrical Characteristics
• Performance Characteristics
• Switching Characteristics
• Pin-to-Pin Output Parameter Guidelines
• Pin-to-Pin Input Parameter Guidelines
• DCM Timing Parameters
Module 4:
Pinout Information
DS031-4 (v2.0) August 1, 2003
225 pages
• Pin Definitions
• Pinout Tables
- CS144 Chip-Scale BGA Package
- FG256 Fine-Pitch BGA Package
- FG456 Fine-Pitch BGA Package
- FG676 Fine-Pitch BGA Package
- BG575 Standard BGA Package
- BG728 Standard BGA Package
- FF896 Flip-Chip Fine-Pitch BGA Package
- FF1152 Flip-Chip Fine-Pitch BGA Package
- FF1517 Flip-Chip Fine-Pitch BGA Package
- BF957Flip-Chip BGA Package
IMPORTANT NOTE: The Virtex-II Platform FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy
navigation in this volume.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031 August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778

1 Page





XC2V4000 pdf, ピン配列
R Virtex™-II Platform FPGAs: Introduction and Overview
Table 1: Virtex-II Field-Programmable Gate Array Family Members
CLB
(1 CLB = 4 slices = Max 128 bits)
Device
System Array
Gates Row x Col.
Slices
Maximum
Distributed
RAM Kbits
Multiplier
Blocks
XC2V40
40K 8 x 8 256
8
4
XC2V80
80K 16 x 8 512
16
8
XC2V250
250K
24 x 16
1,536
48
24
XC2V500
500K
32 x 24
3,072
96
32
XC2V1000
1M
40 x 32 5,120
160
40
XC2V1500 1.5M
48 x 40
7,680
240
48
XC2V2000
2M
56 x 48 10,752
336
56
XC2V3000
3M
64 x 56 14,336
448
96
XC2V4000
4M
80 x 72 23,040
720
120
XC2V6000
6M
96 x 88 33,792
1,056
144
XC2V8000
8M 112 x 104 46,592
1,456
168
Notes:
1. See details in Table 2, “Maximum Number of User I/O Pads”.
SelectRAM Blocks
18 Kbit
Blocks
4
8
24
32
40
48
56
96
120
144
168
Max RAM
(Kbits)
72
144
432
576
720
864
1,008
1,728
2,160
2,592
3,024
Max I/O
DCMs Pads(1)
4 88
4 120
8 200
8 264
8 432
8 528
8 624
12 720
12 912
12 1,104
12 1,108
General Description
The Virtex-II family is a platform FPGA developed for high
performance from low-density to high-density designs that
are based on IP cores and customized modules. The family
delivers complete solutions for telecommunication, wire-
less, networking, video, and DSP applications, including
PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
10 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in
Table 1, the Virtex-II family comprises 11 members, ranging
from 40K to 8M system gates.
Packaging
Offerings include ball grid array (BGA) packages with
0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra-
ditional wire-bond interconnects, flip-chip interconnect is
used in some of the BGA offerings. The use of flip-chip
interconnect offers more I/Os than is possible in wire-bond
versions of the similar packages. Flip-chip construction
offers the combination of high pin count with high thermal
capacity.
Table 2 shows the maximum number of user I/Os available.
The Virtex-II device/package combination table (Table 6 at
the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
technology.
Table 2: Maximum Number of User I/O Pads
Device
Wire-Bond
Flip-Chip
XC2V40
88 -
XC2V80
120 -
XC2V250
200 -
XC2V500
264 -
XC2V1000
328 432
XC2V1500
392 528
XC2V2000
- 624
XC2V3000
516 720
XC2V4000
- 912
XC2V6000
- 1,104
XC2V8000
- 1,108
DS031-1 (v2.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
2


3Pages


XC2V4000 電子部品, 半導体
R Virtex™-II Platform FPGAs: Introduction and Overview
Boundary Scan
Boundary scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II devices that complies with IEEE standards
1149.1 — 1993 and 1532. A system mode and a test mode
are implemented. In system mode, a Virtex-II device per-
forms its intended mission even while executing non-test
boundary-scan instructions. In test mode, boundary-scan
test instructions control the I/O pins for testing purposes.
The Virtex-II Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Configuration
Virtex-II devices are configured by loading data into internal
configuration memory, using the following five modes:
• Slave-serial mode
• Master-serial mode
• Slave SelectMAP mode
• Master SelectMAP mode
• Boundary-Scan mode (IEEE 1532)
A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration
information.
Readback and Integrated Logic Analyzer
Configuration data stored in Virtex-II configuration memory
can be read back for verification. Along with the configura-
tion data, the contents of all flip-flops/latches, distributed
SelectRAM, and block SelectRAM memory resources can
be read back. This capability is useful for real-time debug-
ging.
The Integrated Logic Analyzer (ILA) core and software pro-
vides a complete solution for accessing and verifying
Virtex-II devices.
Virtex-II Device/Package Combinations
and Maximum I/O
Wire-bond and flip-chip packages are available. Table 4 and
Table 5 show the maximum possible number of user I/Os in
wire-bond and flip-chip packages, respectively. Table 6
shows the number of available user I/Os for all device/pack-
age combinations.
• CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
• FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
• FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
• BG denotes standard BGA (1.27 mm pitch).
• BF denotes flip-chip BGA (1.27 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD) and VBATT.
Table 4: Wire-Bond Packages Information
Package
CS144
FG256
Pitch (mm)
0.80 1.00
Size (mm)
12 x 12
17 x 17
I/Os 92 172
FG456
1.00
23 x 23
324
FG676
1.00
27 x 27
484
BG575
1.27
31 x 31
408
BG728
1.27
35 x 35
516
Table 5: Flip-Chip Packages Information
Package
FF896
Pitch (mm)
1.00
Size (mm)
31 x 31
I/Os 624
FF1152
1.00
35 x 35
824
FF1517
1.00
40 x 40
1,108
BF957
1.27
40 x 40
684
DS031-1 (v2.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
5

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部品番号部品説明メーカ
XC2V4000

(XC2Vxxx) Virtex-II Platform FPGAs: Complete Data Sheet

Xilinx
Xilinx

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