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MT70003 の電気的特性と機能

MT70003のメーカーはAeroflex Circuit Technologyです、この部品の機能は「SINGLE CHANNEL ARINC DECODER」です。


製品の詳細 ( Datasheet PDF )

部品番号
MT70003
部品説明
SINGLE CHANNEL ARINC DECODER
メーカ
Aeroflex Circuit Technology
ロゴ

Aeroflex Circuit Technology ロゴ 




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MT70003 Datasheet, MT70003 PDF,ピン配置, 機能
MT70003
SINGLE CHANNEL ARINC DECODER
16/24 bit parallel interface
Automatic address recognition option on
8/10 bits
Single 5V supply with low power
consumption < 50mW
Full MIL operating range
Built in parity and word length error
detection
HIGH/LOW speed programmable
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
1

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MT70003 pdf, ピン配列
MT70003
tPLH
tPLH
tPLH
tPLH
tPLH
DATA READY from RESET DATA READY
(16 bit bus option; data access incomplete; NOT DATA
ENABLE LO; LO pulse on NOT RESET DATA READY
>2 )
DATA READY from TAG VALID (NOT DATA
ENABLE LO; sequence operation)
DATA READY from NOT DATA ENABLE (TAG
VALID HI; NOT RESET DATA READY HI)
DATA READY from NOT DATA ENABLE
TAG VALID from NOT RESET DATA READY (Data
access completed)
ADDRESS RECOGNITION times
ADDRESS RECOGNISED settling time from TAG VALID)
(external recognition MODE SELECT HI)
)
TAG INPUTS settling time from TAG VALID (internal )
recognition MODE SELECT LO)
)
ADDRESS RECOGNISED end of hold time from TAG )
VALID
)
TAG INPUTS end of hold time from TAG VALID
6
4 -0.3
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General
This circuit receives serial data from a buffered ARINC 429 bus into a 32 bit shift register. At the end of
transmission the received word is checked. It is only considered to be “good” if the overall parity is ODD and
the length is 32 bits. If the word fails these checks a TRANSMISSION FAULT flag is set. If the word is
‘good’ the tag bits are loaded into a tag latch and a TAG VALID flag is set. Either internal or external
address recognition can be selected according to the state of MODE SELECT.
If the address is recognised within 4 us time window a 32 bit word latch is updated from the shift register.
Thus the word latch only contains a “good” word whose address has been recognised. The contents of the
word latch can be accessed whenever DATA READY flag is HI. It is available on a parallel trio-state output
highway which is either 16 or 24 bits wide according to the state of 16/24 BUS SELECT. In the former, the
32 bit word is output in 2 halves and the state of output DATAMUX indicates which half is present. In the
latter case bits 1 to 8 (the tag bits) are not available but the remaining 24 bits are presented together.
The user signals his receipt of the ARINC word by pulsing NOT RESET DATA READY low indicating that
data access is complete which cancels TAG VALID and DATA READY.
The user has a whole word transmission time to access the word latch without entering an overrun condition.
When ‘end of word’ is detected an internal sequencer is initiated. Firstly, TAG VALID is examined. If this
is still HI an OVERRUN flag is set. Next the data access logic is initialized and both TAG VALID and
TRANSMISSION FAULT are cancelled.
Once set, the OVERRUN flag is only cancelled by a ‘data access complete’ signal. Thus the presence of an
OVERRUN flag signals that the rate of servicing the word latch is slower than the transmission rate. Note
that DATA READY and DATA MUX always refer to the status of the output data available from the word
latch which cannot be updated unless the user requests it, whereas TAG VALID and TRANSMISSION
FAULT always refer the the latest received word. The tag latch is always updated when TAG VALID is set
but unless this tag is recognised the contents of the trag latch will bear no relationship to the contents of the
word latch.
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
3


3Pages


MT70003 電子部品, 半導体
MT70003
It is anticipated that the 24 bit data bus option will be required and that the data tri-states will be permanently
enabled by wiring NOT DATA ENABLE LO.
If only one specific label is of interest this can be hard wired onto the tag ports conditioned as inputs by
wiring MODE SELECT LO. Then internal address recognition will be performed.
If a range of labels is of interest then MODE SELECT can be wired HI. The tag ports are then conditioned as
outputs. By wiring NOT TAG ENABLE LO and by using some simple external ‘acceptable label’ decode to
drive ADDRESS RECOGNISED only the required transmissions are loaded. Note that in this mode if
ADDRESS RECOGNISED is not connected then every good transmission is loaded into the word latch
irrespective of its label since this input has an ‘on chip’ pull-up transistor.
Several of the pins may not be of interest e.g. OVERRUN, TRANSMISSION FAULT, TAG VALID, DATA
READY, NOT RESET DATA READY, DATA MUX, in which case they need not be connected. This will
not impair the basic function since a good, recognised transmission will be maintained in the word latch until
overwritten by the next good, recognised transmission.
General Processor Systems
It is anticipated that the 16 bit data highway option will be required.
Many users will wire MODE SELECT HI and employ a label identification P.R.O.M. to generate the address
recognition signal. A Direct Memory Access can be performed to transfer wanted data from the word latch
into memory.
If the user requires an indication of the word transmission rate he can externally ‘OR’ TRANSMISSION
FAULT with TAG VALID. The rising edge of such a waveform could be used to trigger a timer.
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
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6 Page

合計 : 6 ページ
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部品番号部品説明メーカ
MT70003

SINGLE CHANNEL ARINC DECODER

Aeroflex Circuit Technology
Aeroflex Circuit Technology

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