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D784927YGF101 の電気的特性と機能

D784927YGF101のメーカーはNECです、この部品の機能は「UPD784927Y」です。


製品の詳細 ( Datasheet PDF )

部品番号
D784927YGF101
部品説明
UPD784927Y
メーカ
NEC
ロゴ

NEC ロゴ 




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D784927YGF101 Datasheet, D784927YGF101 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784927, 784928, 784927Y, 784928Y
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high-
speed, high-performance 16-bit CPU for VCR software servo control.
www.DataSheet4U.com The µPD784927Y and 784928Y are based on the µPD784928 with the addition of an I2C bus interface compatible
with multi-master.
They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer
unit) for software servo control and VCR analog circuits.
Flash memory models, the µPD78F4928 and µPD78F4928Y, are under development.
The functions of the µPD784927 is described in detail in the following User’s Manual. Be sure to read this
manual before designing your system.
µPD784928, 784928Y Subseries User’s Manual - Hardware
: U12648E
78K/IV Series User’s Manual - Instruction
: U10905E
FEATURES
High instruction execution speed realized by 16-bit CPU core
• Minimum instruction execution time: 250 ns (with 8 MHz internal clock)
High internal memory capacity
Item
Part Number µPD784927, 784927Y µPD784928, 784928Y
Internal ROM capacity
96K bytes
128K bytes
Internal RAM capacity
2048 bytes
3584 bytes
VCR analog circuits conforming to VHS Standard
• CTL amplifier
• DFG amplifier
• Reel FG comparator (2 channels)
• RECCTL driver (rewritable) • DPG amplifier
• CSYNC comparator
• CFG amplifier
• DPFG separation circuit (ternary separation circuit)
Timer unit (super timer unit) for servo control
Serial interface : 3 channels
3-wire serial I/O : 2 channels
I2C bus interface: 1 channel
A/D converter: 12 channels (conversion time: 10 µs)
Low-frequency oscillation mode: main system clock frequency = internal clock frequency
Low-power consumption mode: CPU can operate with a subsystem clock.
Supply voltage range: VDD = +2.7 to 5.5 V
Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption
Unless otherwise specified, the µPD784927 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12255EJ2V0DS00 (2nd edition)
Date Published December 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997,1999

1 Page





D784927YGF101 pdf, ピン配列
µPD784927, 784928, 784927Y, 784928Y
FUNCTION LIST (1/2)
Item
Part Number
Internal ROM capacity
Internal RAM capacity
Operating clock
Minimum instruction e x e c u -
tion time
I/O port
www.DataSheet4U.com
Real-time output port
Timer/counter
Capture register
Super
timer unit
VCR special
circuit
General-purpose
timer
PWM output
Serial interface
A/D converter
µPD784927, 784927Y
µPD784928, 784928Y
96K bytes
128K bytes
2048 bytes
3584 bytes
16 MHz (internal clock: 8 MHz)
Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz)
Low power consumption mode : 32.768 kHz (subsystem clock)
250 ns (with 8 MHz internal clock)
input : 20
74
I/O : 54 (including 8 ports for LED direct drive)
11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation)
Timer/counter
TM0 (16 bits)
TM1 (16 bits)
FRC (22 bits)
TM3 (16 bits)
UDC (5 bits)
EC (8 bits)
EDV (8 bits)
Compare register
3
3
2
1
4
1
Capture register
1
6
1
Remark
For HSW signal generation
For CFG signal division
Input signal
CFG
DFG
HSW
VSYNC
CTL
TREEL
SREEL
Number of bits
22
22
16
22
16
22
22
Measurable cycle
125 ns to 524 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
125 ns to 524 ms
Operating edge
↑↓
↑↓
↑↓
↑↓
↑↓
VSYNC separation circuit, HSYNC separation circuit
VISS detection, wide aspect detection circuits
Field identification circuit
Head amplifier switch/chrominance rotation output circuit
Timer
TM2 (16 bits)
TM4 (16 bits)
TM5 (16 bits)
Compare register
1
1 (capture/compare)
1
Capture register
1
16-bit resolution : 3 channels (carrier frequency: 62.5 kHz)
8-bit resolution : 3 channels (carrier frequency: 62.5 kHz)
3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel)
I2C bus interface: 1 channel (µPD784928Y subseries only)
8-bit resolution × 12 channels, conversion time: 10 µs
Data Sheet U12255EJ2V0DS00
3


3Pages


D784927YGF101 電子部品, 半導体
µPD784927, 784928, 784927Y, 784928Y
100-pin plastic QFP (14 × 20 mm)
µPD784927GF-×××-3BA, 784928GF-×××-3BA,
µPD784927YGF-×××-3BA, 784928YGF-×××-3BA
www.DataSheet4U.com
DFGMON/P64/BUZ
DPGMON/P65/HWIN
CFGMON/P66/PWM4
CTLMON/P67/PWM5
P60/STRB/CLO
P61/SCK1/BUZ
P62/SO1
P63/SI1
P37/PWM0
P36/PWM1
P35/SCK2
P34/SO2
P33/SI2/BUSY
VDD
XT1
XT2
VSS
X2
X1
RESET
IC
P32/PTO02
P31/PTO01
P30/PTO00
P87/PTO11
P86/PTO10
SCLNote/P85/PWM3
SDANote/P84/PWM2
P83/ROTC
P82/HASW
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ANI9/P111
ANI8/P110
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
AVREF
AVDD2
P96
P95/KEY4
P94/KEY3
P93/KEY2
P92/KEY1
P91/KEY0
P90/ENV
NMI/P20
INTP0/P21
INTP1/P22
INTP2/23
P00
P01
P02
P03
P04
P05
P06
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
Caution Directly connect the IC (Internally Connected) pins to VSS.
6 Data Sheet U12255EJ2V0DS00

6 Page

合計 : 30 ページ
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部品番号部品説明メーカ
D784927YGF101

UPD784927Y

NEC
NEC

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