n UltraFast™ (10ns typ)
n Operates Off Single 5V Supply or ±5V
n Complementary Output to TTL
n Low Offset Voltage
n No Minimum Input Slew Rate Requirement
n No Power Supply Current Spiking
n Output Latch Capability
n High Speed A/D Converters
■ High Speed Sampling Circuits
■ Line Receivers
■ Extended Range V-to-F Converters
■ Fast Pulse Height/Width Discriminators
■ Zero-Crossing Detectors
■ Current Sense for Switching Regulators
■ High Speed Triggers
■ Crystal Oscillators
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
UltraFast is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TheLT®1016 isanUltraFast10ns comparator that interfaces
directly to TTL/CMOS logic while operating off either ±5V
or single 5V supplies. Tight offset voltage specifications
and high gain allow the LT1016 to be used in precision
applications. Matched complementary outputs further
extend the versatility of this comparator.
A unique output stage provides active drive in both direc-
tions for maximum speed into TTL/CMOS logic or passive
loads, yet does not exhibit the large current spikes found
in conventional output stages. This allows the LT1016 to
remain stable with the outputs in the active region which,
greatly reduces the problem of output “glitching” when
the input signal is slow moving or is low level.
The LT1016 has a LATCH pin which will retain input data
at the outputs, when held high. Quiescent negative power
supply current is only 3mA. This allows the negative supply
pin to be driven from virtually any supply voltage with a
simple resistive divider. Device performance is not affected
by variations in negative supply voltage.
Linear Technology offers a wide range of comparators
in addition to the LT1016 that address different applica-
tions. See the Related Parts section on the back page of
the data sheet.
10MHz to 25MHz Crystal Oscillator
10MHz TO 25MHz
V – LATCH
0 20 0 20
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.
MIN TYP MAX
VOS Input Offset Voltage
RS ≤ 100Ω (Note 2)
● 3.5 mV
Input Offset Voltage Drift
Input Offset Current
IB Input Bias Current
● 13 µA
Input Voltage Range
Single 5V Supply
Common Mode Rejection
Supply Voltage Rejection
–3.75V ≤ VCM ≤ 3.5V
Positive Supply 4.6V ≤ V+ ≤ 5.4V
Positive Supply 4.6V ≤ V+ ≤ 5.4V
Negative Supply 2V ≤ V– ≤ 7V
Small-Signal Voltage Gain
1V ≤ VOUT ≤ 2V
VOH Output High Voltage
V+ ≥ 4.6V
VOL Output Low Voltage
I+ Positive Supply Current
ISINK = 4mA
ISINK = 10mA
I– Negative Supply Current
VIH LATCH Pin Hi Input Voltage
VIL LATCH Pin Lo Input Voltage
IIL LATCH Pin Current
VLATCH = 0V
Propagation Delay (Note 4)
∆VIN = 100mV, OD = 5mV
∆VIN = 100mV, OD = 20mV
● 15 ns
Differential Propagation Delay
(Note 4) ∆VIN = 100mV,
OD = 5mV
Latch Setup Time
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
Note 3: Input bias current (IB) is defined as the average of the two input
Note 4: tPD and ∆tPD cannot be measured in automatic handling equipment
with low values of overdrive. The LT1016 is sample tested with a 1V step
and 500mV overdrive. Correlation tests have shown that tPD and ∆tPD
limits shown can be guaranteed with this test if additional DC tests are
performed to guarantee that all internal bias conditions are correct. For low
overdrive conditions VOS is added to overdrive. Differential propogation
delay is defined as: ∆tPD = tPDLH – tPDHL
Note 5: Electrical specifications apply only up to 5.4V.
Note 6: Input voltage range is guaranteed in part by CMRR testing and
in part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
Note 7: This parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.
Common Mode Considerations
The LT1016 is specified for a common mode range of
–3.75V to 3.5V with supply voltages of ±5V. A more
general consideration is that the common mode range
is 1.25V above the negative supply and 1.5V below the
positive supply, independent of the actual supply voltage.
The criteria for common mode limit is that the output still
responds correctly to a small differential input signal.
Either input may be outside the common mode limit (up
to the supply voltage) as long as the remaining input is
within the specified limit, and the output will still respond
correctly. There is one consideration, however, for inputs
that exceed the positive common mode limit. Propagation
delay will be increased by up to 10ns if the signal input
is more positive than the upper common mode limit and
then switches back to within the common mode range.
This effect is not seen for signals more negative than the
lower common mode limit.
Input Impedance and Bias Current
Input bias current is measured with the output held at
1.4V. As with any simple NPN differential input stage, the
LT1016 bias current will go to zero on an input that is low
and double on an input that is high. If both inputs are less
than 0.8V above V–, both input bias currents will go to
zero. If either input exceeds the positive common mode
limit, input bias current will increase rapidly, approaching
several milliamperes at VIN = V+.
Differential input resistance at zero differential input
voltage is about 10kΩ, rapidly increasing as larger DC
differential input signals are applied. Common mode
input resistance is about 4MΩ with zero differential input
voltage. With large differential input signals, the high input
will have an input resistance of about 2MΩ and the low
input greater than 20MΩ.
Input capacitance is typically 3.5pF. This is measured by
inserting a 1k resistor in series with the input and measur-
ing the resultant change in propagation delay.
LATCH Pin Dynamics
The LATCH pin is intended to retain input data (output
latched) when the LATCH pin goes high. This pin will
float to a high state when disconnected, so a flowthrough
condition requires that the LATCH pin be grounded. To
guarantee data retention, the input signal must be valid at
least 5ns before the latch goes high (setup time) and must
remain valid at least 3ns after the latch goes high (hold
time). When the latch goes low, new data will appear at
the output in approximately 8ns to 10ns. The LATCH pin
is designed to be driven with TTL or CMOS gates. It has
no built-in hysteresis.
Measuring Response Time
The LT1016 is able to respond quickly to fast low level
signals because it has a very high gain-bandwidth prod-
uct (≈50GHz), even at very high frequencies. To properly
measure the response of the LT1016 requires an input
signal source with very fast rise times and exceptionally
clean settling characteristics. This last requirement comes
about because the standard comparator test calls for an
input step size that is large compared to the overdrive
amplitude. Typical test conditions are 100mV step size
with only 5mV overdrive. This requires an input signal
that settles to within 1% (1mV) of final value in only a few
nanoseconds with no ringing or “long tailing.” Ordinary
high speed pulse generators are not capable of generating
such a signal, and in any case, no ordinary oscilloscope
is capable of displaying the waveform to check its fidelity.
Some means must be used to inherently generate a fast,
clean edge with known final value.