DataSheet.jp

MK20DN32VMP5 の電気的特性と機能

MK20DN32VMP5のメーカーはFreescale Semiconductorです、この部品の機能は「ARM CORTEX MCU」です。


製品の詳細 ( Datasheet PDF )

部品番号
MK20DN32VMP5
部品説明
ARM CORTEX MCU
メーカ
Freescale Semiconductor
ロゴ

Freescale Semiconductor ロゴ 




このページの下部にプレビューとMK20DN32VMP5ダウンロード(pdfファイル)リンクがあります。


Total 30 pages
scroll

No Preview Available !

MK20DN32VMP5 Datasheet, MK20DN32VMP5 PDF,ピン配置, 機能
K20 Sub-Family Reference Manual
Supports: MK20DN32VLH5, MK20DX32VLH5, MK20DN64VLH5,
MK20DX64VLH5, MK20DN128VLH5, MK20DX128VLH5,
MK20DN32VMP5, MK20DX32VMP5, MK20DN64VMP5,
MK20DX64VMP5, MK20DN128VMP5, MK20DX128VMP5
Document Number: K20P64M50SF0RM
Rev. 2, Feb 2012

1 Page





MK20DN32VMP5 pdf, ピン配列
Section Number
Contents
Title
Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................45
1.1.1 Purpose.........................................................................................................................................................45
1.1.2 Audience......................................................................................................................................................45
1.2 Conventions..................................................................................................................................................................45
1.2.1 Numbering systems......................................................................................................................................45
1.2.2 Typographic notation...................................................................................................................................46
1.2.3 Special terms................................................................................................................................................46
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................47
2.2 Kinetis Portfolio............................................................................................................................................................47
2.3 K20 Family Introduction...............................................................................................................................................50
2.4 Module Functional Categories......................................................................................................................................50
2.4.1 ARM Cortex-M4 Core Modules..................................................................................................................51
2.4.2 System Modules...........................................................................................................................................52
2.4.3 Memories and Memory Interfaces...............................................................................................................53
2.4.4 Clocks...........................................................................................................................................................53
2.4.5 Security and Integrity modules....................................................................................................................54
2.4.6 Analog modules...........................................................................................................................................54
2.4.7 Timer modules.............................................................................................................................................54
2.4.8 Communication interfaces...........................................................................................................................56
2.4.9 Human-machine interfaces..........................................................................................................................56
2.5 Orderable part numbers.................................................................................................................................................57
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................59
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc.
3


3Pages


MK20DN32VMP5 電子部品, 半導体
Section Number
Title
Page
4.2 System memory map.....................................................................................................................................................131
4.2.1 Aliased bit-band regions..............................................................................................................................132
4.3 Flash Memory Map.......................................................................................................................................................133
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................134
4.4 SRAM memory map.....................................................................................................................................................134
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................135
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................135
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................139
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................141
5.2 Programming model......................................................................................................................................................141
5.3 High-Level device clocking diagram............................................................................................................................141
5.4 Clock definitions...........................................................................................................................................................142
5.4.1 Device clock summary.................................................................................................................................143
5.5 Internal clocking requirements.....................................................................................................................................144
5.5.1 Clock divider values after reset....................................................................................................................145
5.5.2 VLPR mode clocking...................................................................................................................................145
5.6 Clock Gating.................................................................................................................................................................146
5.7 Module clocks...............................................................................................................................................................146
5.7.1 PMC 1-kHz LPO clock................................................................................................................................148
5.7.2 WDOG clocking..........................................................................................................................................148
5.7.3 Debug trace clock.........................................................................................................................................148
5.7.4 PORT digital filter clocking.........................................................................................................................149
5.7.5 LPTMR clocking..........................................................................................................................................149
5.7.6 USB FS OTG Controller clocking...............................................................................................................150
5.7.7 UART clocking............................................................................................................................................150
5.7.8 I2S/SAI clocking..........................................................................................................................................151
5.7.9 TSI clocking.................................................................................................................................................151
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
6 Freescale Semiconductor, Inc.

6 Page

合計 : 30 ページ
PDF ダウンロード

[ MK20DN32VMP5 データシート.PDF ]

データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。

scroll


部品番号部品説明メーカ
MK20DN32VMP5

ARM CORTEX MCU

Freescale Semiconductor
Freescale Semiconductor

www.DataSheet.jp     

|     2020   |  メール    |

    最新        |     Sitemap