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AD7457 の電気的特性と機能
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AD7457のメーカーはAnalog Devicesです、この部品の機能は「100 kSPS 12-Bit ADC」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7457 |
| 部品説明 100 kSPS 12-Bit ADC |
| メーカ Analog Devices |
ロゴ |
このページの下部にプレビューとAD7457ダウンロード（pdfファイル）リンクがあります。 Total 21 pages |
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Low Power, Pseudo Differential, 100 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7457
FEATURES
Specified for VDD of 2.7 V to 5.25 V
Low power:
0.9 mW max at 100 kSPS with VDD = 3 V
3 mW max at 100 kSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface—SPI®-/QSPI™-/
MICROWIRE™-/DSP-compatible
Automatic power-down mode
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD7457 is a 12-bit, low power, successive approximation
(SAR) analog-to-digital converter that features a pseudo
differential analog input. This part operates from a single 2.7 V
to 5.25 V power supply and features throughput rates of up to
100 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold (T/H) amplifier that can handle input frequen-
cies in excess of 1 MHz. The reference voltage for the AD7457 is
applied externally to the VREF pin and can range from 100 mV to
VDD, depending on what suits the application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The SAR architecture of this
part ensures that there are no pipeline delays.
The AD7457 uses advanced design techniques to achieve very
low power dissipation.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
AD7457
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V power supplies.
2. Low power consumption. With a 3 V supply, the AD7457
offers 0.9 mW maximum power consumption for a
100 kSPS throughput rate.
3. Pseudo differential analog input.
4. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. Automatic power-
down after conversion allows the average power consump-
tion to be reduced.
5. Variable voltage reference input.
6. No pipeline delays.
7. Accurate control of the sampling instant via the CS input
and once-off conversion control.
8. ENOB > 10 bits typically with 500 mV reference.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
1 Page
AD7457
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Circuit Information.................................................................... 11
Converter Operation.................................................................. 11
ADC Transfer Function............................................................. 11
Typical Connection Diagram ................................................... 11
REVISION HISTORY
2/05—Rev. 0 to Rev. A
Changes to Table 3............................................................................ 6
Changes to Ordering Guide .......................................................... 17
10/03—Rev. 0: Initial Version
Analog Input ............................................................................... 12
Analog Input Structure.............................................................. 12
Digital Inputs .............................................................................. 13
Reference Section ....................................................................... 13
Serial Interface ............................................................................ 13
Power Consumption .................................................................. 14
Microprocessor Interfacing....................................................... 14
Application Hints ........................................................................... 16
Grounding and Layout .............................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
Rev. A | Page 2 of 20
3Pages
AD7457
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fSCLK2
tCONVERT
t2
t33
t43
t5
t6
t7
t84
tPOWER-UP5
tPOWER-DOWN
Limit at TMIN, TMAX
10
10
16 × tSCLK
1.6
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
7.4
Unit
kHz min
MHz max
µs max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
µs min
Description
tSCLK = 1/fSCLK
CS rising edge to SCLK falling edge setup time
Delay from CS rising edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
Minimum time spent in power-down
1 The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. See Figure 2 and the Serial Interface section.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for the output to
cross 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5 See the Power Consumption section.
CS
SCLK
SDATA
POWER
UP
CONVERT
START
TRACK
TPOWERUP
TACQUISITION
t2
t5
HOLD
AUTOMATIC
POWER DOWN
TRACK
TPOWERUP
TACQUISTION
THREE-STATE
t3 t4
t6
0 0 0 0 DB11 DB10
4 LEADING ZEROS
t8
t7
DB2 DB1 DB0
TPOWERDOWN
THREE-STATE
Figure 2. AD7457 Serial Interface Timing Diagram
Rev. A | Page 5 of 20
6 Page
合計 : 21 ページ |
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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