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AD7623 の電気的特性と機能
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AD7623のメーカーはAnalog Devicesです、この部品の機能は「1.33 MSPS PulSAR ADC」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7623 |
| 部品説明 1.33 MSPS PulSAR ADC |
| メーカ Analog Devices |
ロゴ |
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FEATURES
Throughput: 1.33 MSPS
2.048 V internal reference
Differential input range: ±VREF (VREF up to 2.5 V)
INL: ±1 LSB typical
16-bit resolution with no missing codes
SINAD: 88 dB typical @ 100 kHz
THD: −97 dB typical @ 100 kHz
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
2.5 V single-supply operation
Power dissipation: 45 mW typical @ 1.33 MSPS
48-lead LQFP and LFCSP_VQ packages
Speed upgrade of the AD7677
APPLICATIONS
Medical instruments
High speed data acquisition
Digital signal processing
Communications
Instrumentation
Spectrum analysis
ATE
GENERAL DESCRIPTION
The AD7623 is a 16-bit, 1.33 MSPS, charge redistribution SAR,
fully differential analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. It contains a high
speed 16-bit sampling ADC, an internal conversion clock, an
internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. Power consump-
tion is automatically scaled with throughput, making it ideal
for battery-powered applications. It is available in 48-lead, low
profile quad flat package (LQFP) and a lead frame chip-scale
(LFCSP_VQ) package. Operation is specified from
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
16-Bit, 1.33 MSPS PulSAR® ADC
AD7623
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
REF
REF AMP
SWITCHED
CAP DAC
AD7623
SERIAL
PORT
16
PARALLEL
INTERFACE
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OVDD
OGND
D[15:0]
SER/PAR
BUSY
RD
CS
OB/2C
BYTESWAP
CNVST
Figure 1.
Table 1. PulSAR Selection
Type/kSPS
Pseudo
Differential
True Bipolar
True
Differential
18-Bit
Multichannel/
Simultaneous
100 to 250
AD7651
AD7660/61
AD7663
AD7675
500 to 570
AD7650/52
AD7664/66
AD7665
AD7676
AD7678
AD7679
AD7654
800 to
1000
AD7653
AD7667
AD7671
AD7677
AD7674
AD7655
>1000
AD7621
AD7623
AD7641
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7623 is a 1.33 MSPS, charge redistribution,
16-bit SAR ADC.
2. Superior Linearity.
The AD7623 has no missing 16-bit code.
3. Internal Reference.
The AD7623 has a 2.048 V internal reference with a
typical drift of ±7 ppm/°C.
4. Single-Supply Operation.
The AD7623 operates from a 2.5 V single supply and
typically dissipates 45 mW. Its power dissipation decreases
with the throughput.
5. Serial or Parallel Interface.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interface
arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 Page
AD7623
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Serial Clock Timing Specifications ............................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 15
Circuit Information.................................................................... 15
Converter Operation.................................................................. 15
Transfer Functions...................................................................... 16
Typical Connection Diagram ................................................... 17
REVISION HISTORY
7/05—Revision 0: Initial Version
Analog Inputs ............................................................................. 17
Driver Amplifier Choice ........................................................... 17
Voltage Reference Input ............................................................ 18
Power Supply............................................................................... 19
Power Dissipation vs. Throughput .......................................... 20
Conversion Control ................................................................... 20
Interfaces.......................................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface......................................................................... 21
Serial Interface ............................................................................ 22
Master Serial Interface............................................................... 22
Slave Serial Interface .................................................................. 24
Microprocessor Interfacing....................................................... 26
Application ...................................................................................... 27
Layout .......................................................................................... 27
Evaluating the AD7623 Performance ...................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. 0 | Page 2 of 28
3Pages
AD7623
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
RESET Low to BUSY High Delay2
BUSY High Time from RESET Low2
PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 35).
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES3 (Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay3
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period4
Internal SCLK High4
Internal SCLK Low4
SDOUT Valid Setup Time4
SDOUT Valid Hold Time4
SCLK Last Edge to SYNC Delay4
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert4
CNVST Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES3 (Refer to Figure 40 and Figure 41)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol Min
t1 15
t2 750
t3
t4
t5
t6 10
t7
t8 125
t9 15
t38
t39
t10
t11 2
t12
t13 2
t14
t15
t16
t17
t18 0.5
t19 8
t20 2
t21 3
t22 1
t23 0
t24 0
t25
t26
t27
t28
t29
t30
t31 5
t32 1
t33 5
t34 5
t35 12.5
t36 5
t37 5
Typ Max
701
23
560
1
560
10
600
560
20
15
10
10
10
263
12
See Table 4
500
13
10
10
10
8
1 See the Conversion Control section.
2 See the Digital Interface and RESET sections.
3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 5 of 28
6 Page
合計 : 29 ページ |
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| 部品番号 | 部品説明 | メーカ |
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