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AD7622 の電気的特性と機能
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AD7622のメーカーはAnalog Devicesです、この部品の機能は「2 MSPS PulSAR ADC」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7622 |
| 部品説明 2 MSPS PulSAR ADC |
| メーカ Analog Devices |
ロゴ |
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16-Bit, 1.5 LSB INL, 2 MSPS PulSAR® ADC
AD7622
FEATURES
Throughput
2 MSPS (wideband warp and warp mode)
1.5 MSPS (normal mode)
INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR)
16-bit resolution with no missing codes
Dynamic range: 92.5 dB typical
SINAD: 91 dB minimum @ 20 kHz (VREF = 2.5 V)
THD: −115 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typical drift 8 ppm/°C; TEMP output
Differential input range: ±VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation
70 mW typical @ 2 MSPS with internal REF
2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with other PulSAR 48-lead ADCs
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
GENERAL DESCRIPTION
The AD7622 is a 16-bit, 2 MSPS, charge redistribution SAR,
fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 16-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. It features two
very high sampling rate modes (wideband warp and warp) and
a fast mode (normal) for asynchronous rate applications. The
AD7622 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7622 is available in Pb-free only packages with
operation specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
REF
REF AMP
SWITCHED
CAP DAC
AD7622
SERIAL
PORT 16
PARALLEL
INTERFACE
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OVDD
OGND
D[15:0]
SER/PAR
BUSY
RD
CS
OB/2C
BYTESWAP
WARP NORMAL CNVST
Figure 1.
Table 1. PulSAR 48-Lead ADC Selection
Type/kSPS
100 to
250
500 to
570
650 to
1000
Pseudo
Differential
AD7651,
AD7660,
AD7661
AD7650,
AD7652,
AD7664,
AD7666
AD7653,
AD7667
True Bipolar
AD7610, AD7665 AD7612,
AD7663
AD7671
True
Differential
AD7675 AD7676 AD7677
18-Bit
Multichannel/
Simultaneous
AD7631,
AD7678
AD7679
AD7654
AD7634,
AD7674
AD7655
>1000
AD7621,
AD7622,
AD7623
AD7641,
AD7643
1.50
POSITIVE INL = +0.43 LSB
NEGATIVE INL = –0.49 LSB
1.00
0.50
0
–0.50
–1.00
–1.50
0
16384
32768
CODE
49152
Figure 2. Integral Nonlinearity vs. Code
65536
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 Page
AD7622
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Applications Information .............................................................. 15
Circuit Information.................................................................... 15
Converter Operation.................................................................. 15
Modes of Operation ................................................................... 15
Transfer Functions...................................................................... 16
Typical Connection Diagram........................................................ 17
Analog Inputs.............................................................................. 17
Multiplexed Inputs ..................................................................... 17
Driver Amplifier Choice ........................................................... 18
Voltage Reference Input ............................................................ 19
Power Supply............................................................................... 20
Conversion Control ................................................................... 20
Interfaces.......................................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface......................................................................... 21
Serial interface ............................................................................ 22
Master Serial Interface............................................................... 22
Slave Serial Interface .................................................................. 24
Microprocessor Interfacing....................................................... 26
Application Hints ........................................................................... 27
Layout .......................................................................................... 27
Evaluating the AD7622 Performance ...................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
6/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
3Pages
AD7622
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width
Time Between Conversions (Warp Mode2/Normal Mode3)
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Warp Mode/Normal Mode
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time (Warp Mode/Normal Mode)
Acquisition Time (Warp Mode/Normal Mode)
RESET Pulse Width
RESET Low to BUSY High Delay4
BUSY High Time from RESET Low4
PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 36 )
CNVST Low to Data Valid Delay (Warp Mode/Normal Mode)
Data Valid to BUSY Low Delay
Bus Access Request to Data Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay5
CS Low to SDOUT Delay
CNVST Low to SYNC Delay (Warp Mode/Normal Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period6
Internal SCLK High6
Internal SCLK Low6
SDOUT Valid Setup Time6
SDOUT Valid Hold Time6
SCLK Last Edge to SYNC Delay6
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read After Convert6
CNVST Low to SYNC Asserted Delay (Warp Mode/Normal Mode)
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES (Refer to Figure 40 and Figure 41)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol Min
Typ
Max
t1 15
t2 500/667
t3
701
23
t4
t5 1
t6 10
t7
t8 140/182
t9 15
t38 10
t39 500
360/485
360/485
t10
t11 2
t12
t13 2
360/485
20
15
t14
t15
t16
t17
t18 2
t19 8
t20 2
t21 3
t22 1
t23 0
t24 0
t25
t26
t27
t28
t29
t30
15/135
10
10
10
20
See Table 4
375/500
13
10
10
10
t31 5
t32 1
t33 5
t34 5
t35 12.5
t36 5
t37 5
8
See Notes on next page.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 5 of 28
6 Page
合計 : 29 ページ |
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| 部品番号 | 部品説明 | メーカ |
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