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AD7791 の電気的特性と機能
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AD7791のメーカーはAnalog Devicesです、この部品の機能は「Buffered 24-Bit Sigma-Delta ADC」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7791 |
| 部品説明 Buffered 24-Bit Sigma-Delta ADC |
| メーカ Analog Devices |
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このページの下部にプレビューとAD7791ダウンロード（pdfファイル）リンクがあります。 Total 21 pages |
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Data Sheet
FEATURES
Power
Supply: 2.5 V to 5.25 V operation
Normal: 75 μA max
Power-down: 1 μA max
RMS noise: 1.1 μV at 9.5 Hz update rate
19.5-bit p-p resolution (22 bits effective resolution)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Rail-to-rail input buffer
VDD monitor channel
Temperature range: –40°C to +105°C
10-lead MSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
Low Power, Buffered 24-Bit
Sigma-Delta ADC
AD7791
FUNCTIONAL BLOCK DIAGRAM
GND VDD REFIN(+) REFIN(–)
VDD
CLOCK
AIN(+)
AIN(–)
GND
BUF
-
ADC
AD7791
Figure 1.
SERIAL
INTERFACE
DOUT/RDY
DIN
SCLK
CS
04227-0-001
GENERAL DESCRIPTION
The AD7791 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 24-bit ∑-Δ ADC with one differential input that can be
buffered or unbuffered.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to
1.1 μV at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a reduc-
tion in the current consumption. The update rate, cutoff fre-
frequency, and settling time will scale with the clock frequency.
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 μW maximum. It is housed in a 10-lead MSOP.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 Page
AD7791
TABLE OF CONTENTS
AD7791—Specifications.................................................................. 3
Timing Characteristics, ................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
On-chip Registers ........................................................................... 10
Communications Register (RS1, RS0 = 0, 0) .......................... 10
Status Register (RS1, RS0 = 0, 0;
Power-on/Reset = 0x8C) ........................................................... 11
Mode Register (RS1, RS0 = 0, 1;
Power-on/Reset = 0x02) ............................................................ 11
Filter Register (RS1, RS0 = 1, 0;
Power-on/Reset = 0x04) ............................................................ 12
Data Register (RS1, RS0 = 1, 1;
Power-on/Reset = 0x000000).................................................... 13
ADC Circuit Information.............................................................. 14
Overview...................................................................................... 14
REVISION HISTORY
3/13—Rev. 0 to Rev. A
Moved ESD Caution Section............................................................7
Changes to Figure 13.......................................................................15
Changes to Reference Input Section .............................................18
Updated Outline Dimensions ........................................................20
Changes to Ordering Guide ...........................................................20
8/03—Revision 0: Initial Version
Data Sheet
Noise Performance ..................................................................... 14
Reduced Current Modes ........................................................... 14
Digital Interface .......................................................................... 15
Single Conversion Mode ....................................................... 16
Continuous Conversion Mode ............................................. 16
Continuous Read Mode ........................................................ 17
Circuit Description......................................................................... 18
Analog Input Channel ............................................................... 18
Bipolar/Unipolar Configuration .............................................. 18
Data Output Coding .................................................................. 18
Reference Input........................................................................... 18
VDD Monitor ................................................................................ 19
Grounding and Layout .............................................................. 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
Rev. A | Page 2 of 20
3Pages
Data Sheet
AD7791
TIMING CHARACTERISTICS1, 2
Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,
Input Logic 1 = VDD, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK High Pulsewidth
t4
100
ns min
SCLK Low Pulsewidth
Read Operation
t1 0
ns min
CS Falling Edge to DOUT/RDY Active Time
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.5 V to 3.6 V
t23 0
ns min
SCLK Active Edge to Data Valid Delay4
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.5 V to 3.6 V
t55, 6
10
ns min
Bus Relinquish Time after CS Inactive Edge
80 ns max
t6
100
ns max
SCLK Inactive Edge to CS Inactive Edge
t7
10
ns min
SCLK Inactive Edge to DOUT/RDY High
Write Operation
t8 0
ns min
CS Falling Edge to SCLK Active Edge Setup Time4
t9
30
ns min
Data Valid to SCLK Edge Setup Time
t10 25
ns min
Data Valid to SCLK Edge Hold Time
t11 0
ns min
CS Rising Edge to SCLK Edge Hold Time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 3 and Figure 4.
3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
Rev. A | Page 5 of 20
6 Page
合計 : 21 ページ |
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