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AD7767 の電気的特性と機能
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AD7767のメーカーはAnalog Devicesです、この部品の機能は「128 kSPS/64 kSPS/32 kSPS ADCs」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7767 |
| 部品説明 128 kSPS/64 kSPS/32 kSPS ADCs |
| メーカ Analog Devices |
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24-Bit, 8.5 mW, 109 dB,
128 kSPS/64 kSPS/32 kSPS ADCs
AD7767
FEATURES
Oversampled successive approximation (SAR) architecture
High performance ac and dc accuracy, low power
115.5 dB dynamic range, 32 kSPS (AD7767-2)
112.5 dB dynamic range, 64 kSPS (AD7767-1)
109.5 dB dynamic range, 128 kSPS (AD7767)
−118 dB THD
Exceptionally low power
8.5 mW, 32 kSPS (AD7767-2)
10.5 mW, 64 kSPS (AD7767-1)
15 mW, 128 kSPS (AD7767)
High dc accuracy
24 bits, no missing codes (NMC)
INL: ±3 ppm (typical), ±7.6 ppm (maximum)
Low temperature drift
Zero error drift: 15 nV/°C
Gain error drift: 0.4 ppm/°C
On-chip low-pass FIR filter
Linear phase response
Pass-band ripple: ±0.005 dB
Stop-band attenuation: 100 dB
2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options
Flexible interfacing options
Synchronization of multiple devices
Daisy-chain capability
Power-down function
Temperature range: −40°C to +105°C
APPLICATIONS
Low power PCI/USB data acquisition systems
Low power wireless acquisition systems
Vibration analysis
Instrumentation
High precision medical acquisition
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND MCLK DVDD VDRIVE DGND
VREF+
VIN+
VIN–
REFGND
SUCCESSIVE
APPROXIMATION
ADC
DIGITAL
FIR FILTER
AD7767/
AD7767-1/
AD7767-2
SERIAL INTERFACE
AND
CONTROL LOGIC
SCLK DRDY SDO SDI
Figure 1.
SYNC/PD
CS
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
GENERAL DESCRIPTION
The AD7767/AD7767-1/AD7767-2 are high performance,
24-bit, oversampled SAR analog-to-digital converters (ADCs).
The AD7767/AD7767-1/AD7767-2 combine the benefits of a
large dynamic range and input bandwidth, consuming 15 mW,
10.5 mW, and 8.5 mW power, respectively, and are contained in
a 16-lead TSSOP package.
Ideal for ultralow power data acquisition (such as PCI- and
USB-based systems), the AD7767/AD7767-1/AD7767-2
provide 24-bit resolution. The combination of exceptional SNR,
wide dynamic range, and outstanding dc accuracy make the
AD7767/AD7767-1/AD7767-2 ideally suited for measuring
small signal changes over a wide dynamic range. This is
particularly suitable for applications where small changes on the
input are measured on larger ac or dc signals. In such an
application, the AD7767/AD7767-1/AD7767-2 accurately
gather both ac and dc information.
The AD7767/AD7767-1/AD7767-2 include an on-board digital
filter (complete with linear phase response) that acts to elimi-
nate out-of-band noise by filtering the oversampled input
voltage. The oversampled architecture also reduces front-end
antialias requirements. Other features of the AD7767 include a
SYNC/PD (synchronization/power-down) pin, allowing the
synchronization of multiple AD7767 devices. The addition of
an SDI pin provides the option of daisy chaining multiple
AD7767 devices.
The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply
using a 5 V reference. The devices operate from −40°C to +105°C.
RELATED DEVICES
Table 1. 24-Bit ADCs
Part No. Description
AD7760
2.5 MSPS, 100 dB dynamic range,1 on-board differential
amp and reference buffer, parallel, variable decimation
AD7762/
AD7763
625 kSPS, 109 dB dynamic range,1 on-board differential
amp and reference buffer, parallel/serial, variable
decimation
AD7764
312 kSPS, 109 dB dynamic range,1 on-board differential
amp and reference buffer, variable decimation (pin)
AD7765
156 kSPS, 112 dB dynamic range,1 on-board differential
amp and reference buffer, variable decimation (pin)
AD7766 128 kSPS, 109.5 dB,1 15 mW, 16-bit INL, serial interface
AD7766-1 64 kSPS 112.5 dB,110.5 mW, 16-bit INL, serial interface
AD7766-2 32 kSPS, 115.5 dB,1 8.5 mW, 16-bit INL, serial interface
1 Dynamic range at maximum output data rate.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
1 Page
AD7767
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Related Devices ................................................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
AD7767/AD7767-1/AD7767-2 Transfer Function................ 15
Converter Operation.................................................................. 15
Analog Input Structure.............................................................. 16
REVISION HISTORY
5/10—Rev. B to Rev. C
Changes to Pin 8 Description......................................................... 9
Changes to Table 8.......................................................................... 20
3/09—Rev. A to Rev. B
Changes to tSETTLING Parameter, Table 3.......................................... 5
Changes to Table 7.......................................................................... 17
1/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Change to Intermodulation Distortion (IMD) Parameter and
Integral Nonlinearity Parameter, Table 2 ................................. 3
Changes to Supply and Reference Voltages Section................... 16
Changes to Choosing the SCLK Frequency Section.................. 18
Changes to Figure 24...................................................................... 12
Changes to Driving the AD7767 Section .................................... 20
Changes to Single-Ended Signal Source Section........................ 20
Added Figure 41; Renumbered Sequentially .............................. 20
Change to Figure 42 ....................................................................... 21
Added Table 8; Renumbered Sequentially .................................. 20
Replaced VREF+ Input Signal Section ............................................ 22
Replaced Figure 46 ......................................................................... 22
8/07—Revision 0: Initial Version
Supply and Reference Voltages ................................................. 16
AD7767 Interface ........................................................................... 17
Initial Power-Up ......................................................................... 17
Reading Data............................................................................... 17
Power-Down, Reset, and Synchronization ............................. 17
Daisy Chaining ............................................................................... 18
Reading Data in Daisy-Chain Mode ....................................... 18
Choosing the SCLK Frequency ................................................ 18
Daisy-Chain Mode Configuration and Timing Diagrams ... 19
Driving the AD7767....................................................................... 20
Differential Signal Source ......................................................... 20
Single-Ended Signal Source ...................................................... 20
Antialiasing ................................................................................. 21
Power Dissipation....................................................................... 21
VREF+ Input Signal ....................................................................... 22
Multiplexing Analog Input Channels ...................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Rev. C | Page 2 of 24
3Pages
AD7767
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, common-mode input = VREF/2, TA = −40°C (TMIN) to +105°C (TMAX),
unless otherwise noted.1
Table 3.
Parameter
DRDY OPERATION
t1
t2 2
t32
t4
t5
tREAD 3
tDRDY3
Read OPERATION
t6
t7
t8
t9
t10
t11
tSCLK
t12
t13
Read OPERATION WITH CS LOW
t14
t15
DAISY-CHAIN OPERATION
t16
t17
SYNC/PD OPERATION
t18
t19
t20
t21
tSETTLING3
Limit at tMIN, tMAX Unit
Description
510
100
900
265
128
71
294
435
492
tDRDY − t5
n × 8 × tMCLK
ns typ
ns min
ns max
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
MCLK rising edge to DRDY falling edge
MCLK high pulse width
MCLK low pulse width
MCLK rising edge to DRDY rising edge (AD7767)
MCLK rising edge to DRDY rising edge (AD7767-1)
MCLK rising edge to DRDY rising edge (AD7767-2)
DRDY pulse width (AD7767)
DRDY pulse width (AD7767-1)
DRDY pulse width (AD7767-2)
DRDY low period, read data during this period
DRDY period
0 ns min DRDY falling edge to CS setup time
6 ns max CS falling edge to SDO tristate disabled
60 ns max Data access time after SCLK falling edge (VDRIVE = 1.7 V)
50 ns max Data access time after SCLK falling edge (VDRIVE = 2.3 V)
25 ns max Data access time after SCLK falling edge (VDRIVE = 2.7 V)
24 ns max Data access time after SCLK falling edge (VDRIVE = 3.0 V)
10 ns min SCLK falling edge to data valid hold time (VDRIVE = 3.6 V)
10 ns min SCLK high pulse width
10 ns min SCLK low pulse width
1/t8 sec min Minimum SCLK period
6 ns max Bus relinquish time after CS rising edge
0 ns min CS rising edge to DRDY rising edge
0 ns min DRDY falling edge to data valid setup time
0 ns max DRDY rising edge to data valid hold time
1 ns min SDI valid to SCLK falling edge setup time
2 ns max SCLK falling edge to SDI valid hold time
1
20
1
510
(592 × n) + 2
ns typ
ns typ
ns min
ns typ
tMCLK
SYNC/PD falling edge to MCLK rising edge
MCLK rising edge to DRDY rising edge going into SYNC/PD mode
SYNC/PD rising edge to MCLK rising edge
MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode
Filter settling time after a reset or power-down
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V.
2 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum
MCLK frequency is 1.024 MHz.
3 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.
Rev. C | Page 5 of 24
6 Page
合計 : 25 ページ |
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| 部品番号 | 部品説明 | メーカ |
| AD776 | 16-Bit 100 kSPS Oversampling ADC | Analog Devices |
| AD7760 | 2.5 MSPS 20-Bit ADC | Analog Devices |
| AD7761 | Simultaneous Sampling ADC | Analog Devices |
| AD7762 | With On-Chip Buffer 625 KSPS | Analog Devices |