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AD7656A の電気的特性と機能
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AD7656AのメーカーはAnalog Devicesです、この部品の機能は「Simultaneous Sampling Bipolar 16-Bit ADC」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7656A |
| 部品説明 Simultaneous Sampling Bipolar 16-Bit ADC |
| メーカ Analog Devices |
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Data Sheet
250 kSPS, 6-Channel, Simultaneous
Sampling, Bipolar 16-Bit ADC
AD7656A
FEATURES
6 independent analog-to-digital converters (ADCs)
True bipolar analog inputs
Pin-/software-selectable ranges: ±10 V or ±5 V
Fast throughput rate: 250 kSPS
iCMOS® process technology
Low power: 140 mW at 250 kSPS with 5 V supplies
Wide input bandwidth
86.5 dB SNR at 50 kHz input frequency
On-chip reference and reference buffers
Parallel, serial, and daisy-chain interface modes
High speed serial interface
Serial peripheral interface (SPI)/QSPI™/MICROWIRE®/DSP
compatible
Power-down mode: 100 mW maximum
64-lead LQFP
Improved power supply sequencing (PSS) robustness
APPLICATIONS
Power line monitoring systems
Instrumentation and control systems
Multi-axis positioning systems
FUNCTIONAL BLOCK DIAGRAM
VDD CONVST A CONVST B CONVST C AVCC DVCC
REF
V1 T/H
BUF
CLK
OSC
CONTROL
LOGIC
16-BIT SAR
OUTPUT
DRIVERS
V2 T/H
V3 T/H
BUF
16-BIT SAR
16-BIT SAR
V4 T/H
V5 T/H
BUF
16-BIT SAR
16-BIT SAR
OUTPUT
DRIVERS
OUTPUT
DRIVERS
OUTPUT
DRIVERS
V6 T/H
VSS
16-BIT SAR
AD7656A
AGND DGND
Figure 1.
CS
SER/PAR/SEL
VDRIVE
STBY
DB8/DOUT A
SCLK
DB9/DOUT B
DB10/DOUT C
DATA/
CONTROL
LINES
RD
WR/REFEN/DIS
GENERAL DESCRIPTION
The AD7656A1 contains six 16-bit, fast, low power, successive
approximation analog-to-digital converters (ADCs) all in the
one package that is designed on the iCMOS® process (industrial
CMOS). iCMOS is a process combining high voltage silicon
with submicron CMOS and complementary bipolar technologies.
It enables the development of a wide range of high performance
analog ICs, capable of 33 V operation in a footprint that no
previous generation of high voltage devices could achieve. Unlike
analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, which dramatically reduces power
consumption and package size.
The AD7656A features throughput rates of up to 250 kSPS. It
contains wide bandwidth (12 MHz), track-and-hold amplifiers
that can handle input frequencies up to 12 MHz.
The conversion process and data acquisition are controlled
using CONVST x signals and an internal oscillator. Three
CONVST x pins (CONVST A, CONVST B, and CONVST C)
allow independent, simultaneous sampling of the three ADC
pairs. The AD7656A has a high speed parallel and serial interface,
allowing the device to interface with microprocessors or digital
signal processors (DSPs). In serial interface mode, the AD7656A
has a daisy-chain feature that allows multiple ADCs to connect
to a single serial interface. The AD7656A can accommodate
true bipolar input signals in the ±4 × VREF range and ±2 × VREF
range. The AD7656A also contains an on-chip 2.5 V reference.
Multifunction pin names may be referenced by their relevant
function only.
PRODUCT HIGHLIGHTS
1. Six 16-bit, 250 kSPS ADCs on board.
2. Six true bipolar, high impedance analog inputs.
3. Parallel and high speed serial interfaces.
1 Protected by U.S. Patent No. 6,731,232.
Rev. 0
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 Page
AD7656A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Power Supply Sequencing ........................................................... 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 13
REVISION HISTORY
12/13—Revision 0: Initial Version
Data Sheet
Theory of Operation ...................................................................... 15
Converter Details ....................................................................... 15
ADC Transfer Function............................................................. 16
Reference Section ....................................................................... 16
Typical Connection Diagram ................................................... 16
Driving the Analog Inputs ........................................................ 17
Interface Section ......................................................................... 17
Software Selection of ADCs...................................................... 19
Serial Read Operation................................................................ 21
Daisy-Chain Mode (DCEN = 1, SER/PAR/SEL = 1) ............. 21
Application Hints ........................................................................... 24
Layout .......................................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
Rev. 0 | Page 2 of 28
3Pages
Data Sheet
AD7656A
TIMING SPECIFICATIONS
AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the
±4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V, and for the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to
−16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and
timed from a voltage level of 1.6 V.
Table 2.
Parameter
PARALLEL INTERFACE MODE
tCONVERT
tQUIET
tACQ
t1
t10
tWAKE-UP
PARALLEL WRITE OPERATION
t11
t12
t13
t14
t15
PARALLEL READ OPERATION
t2
t3
t4
t5
t6
t7
t8
t9
SERIAL INTERFACE MODE
fSCLK
t16
t172
t18
t19
t20
t21
Limit at TMIN, TMAX
VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V
33
150 150
550 550
60 60
25 25
22
25 25
15 15
00
55
55
55
00
00
00
45 36
45 36
10 10
12 12
66
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
Unit
µs typ
ns min
ns min
ns min
ns min
ms max
µs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
Description1
Conversion time, internal clock
Minimum quiet time required between bus relinquish
and start of next conversion
Acquisition time
CONVST x high to BUSY high
Minimum CONVST x low pulse
STBY rising edge to CONVST x rising edge, not
shown in figures
Partial power-down mode
WR pulse width
CS to WR setup time
CS to WR hold time
Data setup time before WR rising edge
Data hold after WR rising edge
BUSY to RD delay
CS to RD setup time
CS to RD hold time
RD pulse width
Data access time after RD falling edge
Data hold time after RD rising edge
Bus relinquish time after RD rising edge
Minimum time between reads
Frequency of serial read clock
Delay from CS until SDATA three-state disabled
Data access time after SCLK rising edge/CS falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time after SCLK falling edge
CS rising edge to SDATA high impedance
1 Multifunction pin names may be referenced by their relevant function only.
2 A buffer is used on the data output pins for this measurement.
200µA
IOL
TO OUTPUT
PIN CL
25pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 28
6 Page
合計 : 29 ページ |
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| 部品番号 | 部品説明 | メーカ |
| AD7656 | (AD7656 - AD7658) Bipolar 12/14/16-Bit ADC | Analog Devices |
| AD7656-1 | 16-/14-/12-Bit ADC | Analog Devices |
| AD7656A | Simultaneous Sampling Bipolar 16-Bit ADC | Analog Devices |
| AD7656A-1 | 16-Bit ADC | Analog Devices |