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AD7262 の電気的特性と機能
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AD7262のメーカーはAnalog Devicesです、この部品の機能は「Simultaneous Sampling SAR ADC」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7262 |
| 部品説明 Simultaneous Sampling SAR ADC |
| メーカ Analog Devices |
ロゴ |
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Data Sheet
1 MSPS, 12-Bit, Simultaneous Sampling
SAR ADC with PGA and Four Comparators
AD7262
FEATURES
Dual simultaneous sampling 12-bit, 2-channel analog-to-
digital converter (ADC)
True differential analog inputs
Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,
×24, ×32, ×48, ×64, ×96, ×128
Throughput rate per ADC
1 MSPS for AD7262
500 kSPS for AD7262-5
Analog input impedance: >1 GΩ
Wide input bandwidth
−3 dB bandwidth: 1.7 MHz at gain = 2
4 on-chip comparators
SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32
Device offset calibration, system gain calibration
On-chip reference: 2.5 V
−40°C to +105°C operation
High speed serial interface
SPI/QSPI™/MICROWIRE/DSP compatible
48-lead LFCSP and LQFP
GENERAL DESCRIPTION
The AD7262/AD7262-5 are dual, 12-bit, high speed, low power,
successive approximation ADCs that operate from a single 5 V
power supply. The AD7262 features throughput rates of up to
1 MSPS per on-chip ADC. The AD7262-5 features throughput
rates of up to 500 kSPS. Two complete ADC functions allow
simultaneous sampling and conversion of two channels. Each
ADC is preceded by a true differential analog input with a PGA.
There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12,
×16, ×24, ×32, ×48, ×64, ×96, and ×128.
The AD7262/AD7262-5 contain four comparators. Comparator A
and Comparator B are optimized for low power, while Compara-
tor C and Comparator D have fast propagation delays. The
AD7262/AD7262-5 feature a calibration function to remove any
device offset error and programmable gain adjust registers to allow
for input path (for example, sensor) offset and gain compensation.
The AD7262/AD7262-5 have an on-chip 2.5 V reference that
can be disabled if an external referenceis preferred.
The AD7262/AD7262-5 are ideally suited for monitoring small
amplitude signals from a variety of sensors. They include all the
functionality needed for monitoring theposition feedbacksignals
from a variety of analog encoders used in motor control systems.
FUNCTIONAL BLOCK DIAGRAM
AVCC
VREFA
REF BUF
AD7262
12-BIT
VA+
VA–
PGA
T/H
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
DOUTA
CONTROL
LOGIC
VB+
VB–
VREFB
CA_CBVCC
CA+
CA–
CB+
CB–
CA_CB_GND
CC_CDVCC
CC+
CC–
CD+
CD–
CC_CD_GND
PGA
12-BIT
T/H
SUCCESSIVE
OUTPUT
APPROXIMATION DRIVERS
ADC
BUF
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
COMP
OUTPUT
DRIVERS
SCLK
CAL
CS
REFSEL
G0
G1
G2
G3
VDRIVE
DOUTB
PD0/DIN
PD1
PD2
COUTA
COUTB
COUTC
COUTD
AGND
Figure 1.
DGND
PRODUCT HIGHLIGHTS
1. Integrated PGA with a variety of flexible gain settings to
allow detection and conversion of low level analog signals.
2. Each PGA is followed by a dual simultaneous sampling
ADC, featuring throughput rates of 1 MSPS per ADC for
the AD7262. The conversion results of both ADCs are
simultaneously available on separate datalines or in succes-
sion on one data line if only oneserial port is available.
3. Four integrated comparators that can be used to count
signals from pole sensors in motor control applications.
4. Internal 2.5 V reference.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property oftheir respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 78 1.32 9.47 00 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technica l Support
www.analog.com
1 Page
AD7262
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 6
Timing Diagram ........................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Circuit Information.................................................................... 15
Comparators................................................................................ 15
Operation..................................................................................... 15
Analog Inputs.............................................................................. 15
VDRIVE ............................................................................................ 16
Reference ..................................................................................... 17
Typical Connection Diagrams.................................................. 17
REVISION HISTORY
11/2016—Rev. A to Rev. B
Change to Figure 4 ........................................................................... 8
Change to Pin 31, 32 Description, Table 4 .................................... 9
Changes to Serial Interface Section.............................................. 25
Changes to Figure 34 and Figure 34 Caption ............................. 26
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
8/2015—Rev. 0 to Rev. A
Changed ADSP-BF53x to ADSP-BF531..................... Throughout
Data Sheet
Application Details..................................................................... 20
Modes of Operation ....................................................................... 22
Pin-Driven Mode ....................................................................... 22
Gain Selection............................................................................. 22
Power-Down Modes .................................................................. 22
Control Register ......................................................................... 23
On-Chip Registers...................................................................... 24
Serial Interface ................................................................................ 25
Calibration....................................................................................... 27
Internal Offset Calibration........................................................ 27
Adjusting the Offset Calibration Registers................................. 28
System Gain Calibration............................................................ 28
Microprocessor Interfacing........................................................... 29
AD7262/AD7262-5 to ADSP-BF531 ....................................... 29
Application Hints ........................................................................... 30
Grounding and Layout .............................................................. 30
PCB Design Guidelines for LFCSP .......................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Changes to Table 4.............................................................................9
Change to Serial Interface Section ............................................... 25
Changes to Figure 34 and Figure 34 Caption ............................. 26
Change to Microprocessor Interfacing Section and Figure 37. 29
Changes to AD7262/AD7262-5 to ADSP-BF531 Section......... 29
Updated Outline Dimensions....................................................... 31
7/2008—Revision 0: Initial Version
Rev. B | Page 2 of 32
3Pages
Data Sheet
AD7262
Parameter
Min
Typ Max
Unit Test Conditions/Comments
POWER REQUIREMENTS
Digital inputs = 0 V or VDRIVE
AVCC
CA_CBVCC, CC_CDVCC
VDRIVE
IDD
ADC Normal Mode (Static)
4.75 5.25 V
2.7 5.25 V
2.7 5.25 V
20 31.5
mA AVCC = 5.25 V
ADC Normal Mode (Dynamic)
Shutdown Mode
23 33.3
0.5 1
mA AVCC = 5.25 V
μA AVCC = 5.25 V, ADCs and comparators
powered down
Power Dissipation
ADC Normal Mode (Static)
105 165
mW
ADC Normal Mode (Dynamic)
120 175
mW
Shutdown Mode
2.625
5.25
µW
1 These specifications were determined without the use of the gain calibration feature.
2 See the Terminology section.
3 Samples tested during initial release to ensure compliance; they are not subject to production testing.
4 For PGA gain = 1; to use the full analog input range (VCM ± VREF/2) of the AD7262, the VCM voltage should be dropped to lie within a range from 1.95 V to 2.05 V.
5 Refers to Pin VREFA or Pin VREFB.
6 This specification includes the IDD for both comparators. The IDD per comparator is the specified value divided by two.
Rev. B | Page 5 of 32
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| AD7262 | Simultaneous Sampling SAR ADC | Analog Devices |
| AD7264 | Simultaneous Sampling SAR ADC | Analog Devices |
| AD7265 | Differential Input/ Dual 1 MSPS/ 12-Bit/ 3-Channel SAR ADC | Analog Devices |
| AD7266 | Differential Input/ Dual 2 MSPS/ 12-Bit/ 3-Channel SAR ADC | Analog Devices |