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AD7761 の電気的特性と機能
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AD7761のメーカーはAnalog Devicesです、この部品の機能は「Simultaneous Sampling ADC」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD7761 |
| 部品説明 Simultaneous Sampling ADC |
| メーカ Analog Devices |
ロゴ |
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Data Sheet
8-Channel, 16-Bit, Simultaneous Sampling
ADC with Power Scaling, 110.8 kHz BW
AD7761
FEATURES
Linear phase digital filter
Precision ac and dc performance
8-channel simultaneous sampling
256 kSPS ADC output data rate per channel
97.7 dB dynamic range
110.8 kHz input bandwidth (−3 dB bandwidth (BW))
–120 dB THD, typical
±1 LSB INL, ±1 LSB offset error, ±5 LSB gain error
Optimized power dissipation vs. noise vs. input bandwidth
Low latency sinc5 filter
Wideband brick wall filter: ±0.005 dB ripple to 102.4 kHz
Analog input precharge buffers
Power supply
AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V
IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
64-lead LQFP package, no exposed pad
Temperature range: −40°C to +105°C
Selectable power, speed, and input bandwidth
Fast: highest speed; 110.8 kHz BW, 51.5 mW per channel
Median: half speed, 55.4 kHz BW, 27.5 mW per channel
Focus: lowest power, 13.8 kHz BW, 9.375 mW per channel
Input BW range: dc to 110.8 kHz
Programmable input bandwidth/sampling rates
Cyclic redundancy check (CRC) error checking on data interface
Daisy-chaining
APPLICATIONS
Data acquisition systems: USB/PXI/Ethernet
Instrumentation and industrial control loops
Audio test and measurement
Vibration and asset condition monitoring
3-phase power quality analysis
Sonar
High precision medical electroencephalogram (EEG)/
electromyography (EMG)/electrocardiogram (ECG)
FUNCTIONAL BLOCK DIAGRAM
AVDD1A,
AVDD1B REFx+ REFx–
AVDD2A, REGCAPA,
AVDD2B REGCAPB DGND IOVDD DREGCAP
VCM
BUFFERED
VCM
VCM
PRECHARGE
×8 REFERENCE
BUFFERS
1.8V
LDO
AIN0+
CH 0
AIN0–
AIN1+
CH 1
AIN1–
AIN2+
CH 2
AIN2–
AIN3+
CH 3
AIN3–
AIN4+
CH 4
AIN4–
AIN5+
CH 5
AIN5–
AIN6+
CH 6
AIN6–
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
Σ-∆
ADC
DIGITAL
FILTER
ENGINE
SINC5
LOW LATENCY
FILTER
WIDEBAND
LOW RIPPLE
FILTER
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
1.8V
LDO
ADC
OUTPUT
DATA
SERIAL
INTERFACE
SPI
CONTROL
INTERFACE
SYNC_IN
SYNC_OUT
START
RESET
FORMAT1
FORMAT0
DRDY
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
ST0/CS
ST1/SCLK
DEC0/SDO
DEC1/SDI
AIN7+
CH 7
AIN7–
P Σ-∆
P ADC
×16 ANALOG INPUT
PRECHARGE BUFFERS (P)
OFFSET,
GAIN PHASE
CORRECTION
AD7761
PIN/SPI
AVSS
XTAL2/MCLK
Figure 1.
XTAL1
MODE3/GPIO3 FILTER/GPIO4
TO
MODE0/GPIO0
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 Page
AD7761
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .......................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
Timing Specifications .................................................................. 9
1.8 V IOVDD Timing Specifications....................................... 10
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 19
Terminology .................................................................................... 25
Theory of Operation ...................................................................... 26
Clocking, Sampling Tree, and Power Scaling ............................. 26
Noise Performance and Resolution.......................................... 27
Applications Information .............................................................. 29
Power Supplies ............................................................................ 30
Device Configuration ................................................................ 31
Pin Control Mode....................................................................... 31
SPI Control.................................................................................. 34
SPI Control Functionality ......................................................... 35
SPI Control Mode Extra Diagnostic Features ........................ 37
Circuit Information ........................................................................ 38
Core Signal Chain....................................................................... 38
Analog Inputs.............................................................................. 39
VCM............................................................................................. 40
Reference Input........................................................................... 40
Clock Selection ........................................................................... 40
Digital Filtering........................................................................... 40
Decimation Rate Control .......................................................... 42
Antialiasing ................................................................................. 42
Calibration................................................................................... 43
Data Interface.................................................................................. 45
Setting the Format of Data Output .......................................... 45
ADC Conversion Output: Header and Data .......................... 46
Functionality ................................................................................... 54
GPIO Functionality.................................................................... 54
Register Map Details (SPI Control) ............................................. 55
Register Map ............................................................................... 55
Channel Standby Register ......................................................... 57
Channel Mode A Register ......................................................... 57
Channel Mode B Register ......................................................... 58
Channel Mode Select Register.................................................. 58
Power Mode Select Register...................................................... 59
General Device Configuration Register .................................. 59
Data Control: Soft Reset, Sync, and Single-Shot Control
Register ........................................................................................ 60
Interface Configuration Register.............................................. 61
Digital Filter RAM Built in Self Test (BIST) Register............ 61
Status Register............................................................................. 62
Revision Identification Register ............................................... 62
GPIO Control Register .............................................................. 62
GPIO Write Data Register......................................................... 63
GPIO Read Data Register.......................................................... 63
Analog Input Precharge Buffer Enable Register Channel 0 to
Channel 3 .................................................................................... 64
Analog Input Precharge Buffer Enable Register Channel 4 to
Channel 7 .................................................................................... 64
Positive Reference Precharge Buffer Enable Register............ 65
Negative Reference Precharge Buffer Enable Register .......... 65
Offset Registers........................................................................... 65
Gain Registers ............................................................................. 66
Sync Phase Offset Registers ...................................................... 66
ADC Diagnostic Receive Select Register ................................ 66
ADC Diagnostic Control Register ........................................... 67
Modulator Delay Control Register........................................... 68
Chopping Control Register....................................................... 68
Outline Dimensions ....................................................................... 69
Ordering Guide .......................................................................... 69
REVISION HISTORY
4/16—Revision 0: Initial Version
Rev. 0 | Page 2 of 69
3Pages
Data Sheet
Parameter
EXTERNAL REFERENCE
Reference Voltage
Absolute Reference Voltage Limits2
Average Reference Current
Average Reference Current Drift
Common-Mode Rejection
DIGITAL FILTER RESPONSE
Low Ripple Wideband Filter
Decimation Rate
Group Delay
Settling Time
Pass-Band Ripple2
Pass Band
Stop Band Frequency
Stop Band Attenuation
Sinc5 Filter
Decimation Rate
Group Delay
Settling Time
Pass Band
REJECTION
AC Power Supply Rejection Ratio
(PSRR)
AVDD1
AVDD2
IOVDD
DC PSRR
AVDD1
AVDD2
IOVDD
Analog Input Common-Mode
Rejection Ratio (CMRR)
DC
AC
Crosstalk
CLOCK
Crystal Frequency
External Clock (MCLK)
Duty Cycle
MCLK Pulse Width2
Logic Low
Logic High
CMOS Clock Input Voltage
High, VINH
Low, VINL
Test Conditions/Comments
VREF = (REFx+) − (REFx−)
Precharge reference buffers off
Precharge reference buffers on
Fast mode
Precharge reference buffers off
Precharge reference buffers on
Fast mode
Precharge reference buffers off
Precharge reference buffers on
Min
1
AVSS −
0.05
AVSS
FILTER = 0
Up to six selectable decimation rates
Latency
Complete settling
32
±0.005 dB bandwidth
−0.1 dB bandwidth
−3 dB bandwidth
Attenuation > 105 dB
FILTER = 1
Up to six selectable decimation rates
Latency
Complete settling
−3 dB bandwidth
32
VIN = 0.1 V, AVDD1 = 5 V, AVDD2 =
5 V, IOVDD = 2.5 V
VIN = 1 V
VIN = 0.1 V
Up to 10 kHz
−0.5 dBFS input on adjacent channels
See the Clock Selection section
For data sheet performance
Functionality
See the logic inputs parameter
8
12.2
12.2
Rev. 0 | Page 5 of 69
AD7761
Typ Max
Unit
AVDD1 − AVSS V
AVDD1 + 0.05 V
AVDD1
V
±72 μA/V/channel
±16 μA/V/channel
±1.7 nA/V/°C
±49 nA/V/°C
95 dB
34/ODR
68/ODR
0.4 × ODR
0.409 × ODR
0.433 × ODR
0.499 × ODR
105
1024
±0.005
3/ODR
7/ODR
0.204 × ODR
1024
sec
sec
dB
Hz
Hz
Hz
Hz
dB
sec
sec
Hz
90
100
75
100
118
90
95
95
−120
32.768
32.768
50:50
34
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
MHz
%
ns
ns
6 Page
合計 : 30 ページ |
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